Proceedings ArticleDOI
Competitive and cost effective high-k based 28nm CMOS technology for low power applications
Franck Arnaud,Aaron Thean,Manfred Eller,M. Lipinski,Young Way Teh,Martin Ostermayr,K. Kang,Nam-Sung Kim,Kazuya Ohuchi,J.-P. Han,Deleep R. Nair,Jenny Lian,S. Uchimura,S. Kohler,S. Miyaki,Paulo Ferreira,J-H. Park,Masafumi Hamaguchi,Katsura Miyashita,R. Augur,Qintao Zhang,K. Strahrenberg,S. ElGhouli,J. Bonnouvrier,Fumiyoshi Matsuoka,Richard Lindsay,J. Sudijono,Frank Scott Johnson,JiYeon Ku,M. Sekine,An L. Steegen,Ron Sampson +31 more
- pp 1-4
TLDR
In this article, the authors present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal gate-first architecture.Abstract:
In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm2, and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm2) has a demonstrated Static Noise Margin (SNM) of 213mV at 1V. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT∼2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k∼2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.read more
Citations
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Journal ArticleDOI
Process Technology Variation
K. Kuhn,Martin D. Giles,D. Becher,Pramod Kolar,A. Kornfeld,Roza Kotlyar,S. T. Ma,A. Maheshwari,S. Mudanai +8 more
TL;DR: The importance of process variation in modern transistor technology is discussed, front-end variation sources are reviewed, device and circuit variation measurement techniques are presented, and recent intrinsic transistor variation performance from the literature is compared.
Journal ArticleDOI
SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS
Brian Zimmer,Seng Oon Toh,Huy Vo,Yunsup Lee,Olivier P. Thomas,Krste Asanovic,Borivoje Nikolic +6 more
TL;DR: In this article, the authors use importance sampling of dynamic failure metrics to quantify and analyze the effect of different assist techniques, array organization, and timing on Vmin at design time, and demonstrate that the most effective technique for reducing SRAM Vmin is the negative bitline write assist.
Proceedings ArticleDOI
Challenges in the characterization and modeling of BTI induced variability in metal gate / High-k CMOS technologies
Andreas Kerber,T. Nigam +1 more
TL;DR: In this paper, a parallel BTI testing procedure is introduced for discrete MG/HK devices to demonstrate a correlation between time-zero VT and ΔVT and illustrate the minor impact of BTI induced variability on post-stress VT distributions relevant for modeling the circuit aging.
Journal ArticleDOI
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
Taejoong Song,Woojin Rim,Sunghyun Park,Yongho Kim,Giyong Yang,Hoonki Kim,Sanghoon Baek,Jong-Hoon Jung,Bongjae Kwon,Sungwee Cho,Hyun-Taek Jung,Yongjae Choo,Jae-Seung Choi +12 more
TL;DR: The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage (VMIN) and assist overheads.
Journal ArticleDOI
A Comprehensive Benchmark and Optimization of 5-nm Lateral and Vertical GAA 6T-SRAMs
Trong Huynh-Bao,Sushil Sakhare,D. Yakimets,Julien Ryckaert,Aaron Thean,Abdelkarim Mercha,Diederik Verkest,Piet Wambacq +7 more
TL;DR: In this paper, an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors and lateral GAA transistors (LFETs) using 5-nm node design rules is presented.
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