Proceedings ArticleDOI
32nm general purpose bulk CMOS technology for high performance applications at low voltage
Franck Arnaud,Jinping Liu,Y.M. Lee,K.Y. Lim,S. Kohler,J. Chen,B.K. Moon,C.W. Lai,M. Lipinski,L. Sang,Fernando Guarin,C. Hobbs,Paulo Ferreira,Kazuya Ohuchi,J. Li,H. Zhuang,P. Mora,Qintao Zhang,Deleep R. Nair,D.H. Lee,K.K. Chan,S. Satadru,S. Yang,J. Koshy,W. Hayter,M. Zaleski,D.V. Coolbaugh,H.W. Kim,Y.C. Ee,J. Sudijono,Aaron Thean,M. Sherony,S. Samavedam,M. Khare,C. Goldberg,A. Steegen +35 more
- pp 1-4
TLDR
In this paper, a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack is presented for the first time, and a Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay.Abstract:
This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.read more
Citations
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Journal ArticleDOI
Impact of Metal Gate Granularity on Threshold Voltage Variability: A Full-Scale Three-Dimensional Statistical Simulation Study
TL;DR: In this paper, the effect of grain size on both the magnitude of the variability and the shape of the corresponding statistical distribution was investigated in isolation and in combination with random discrete dopants and line-edge roughness.
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The BubbleWrap many-core: popping cores for sequential acceleration
TL;DR: This paper proposes Dynamic Voltage Scaling for Aging Management (DVSAM) - a new scheme for managing processor aging to attain higher performance or lower power consumption and introduces the BubbleWrap many-core, a novel architecture that makes extensive use of DVSAM.
Journal ArticleDOI
CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations
TL;DR: In this paper, the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors are discussed.
Journal ArticleDOI
Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node
Changhwan Shin,Min Hee Cho,Yasumasa Tsukamoto,Bich-Yen Nguyen,Carlos Mazure,Borivoje Nikolic,Tiehui Liu +6 more
TL;DR: In this article, the performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFLETs via 3-D device simulation with atomistic doping profiles.
Journal ArticleDOI
Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance
TL;DR: In this paper, the impact of parasitic capacitances on the circuit-level performance for logic applications is analyzed, and the Si complementary metaloxide-semiconductor roadmap projection is revisited beyond 32-nm technology with different device design scenarios examined.
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