College of Engineering, Pune

About: College of Engineering, Pune is a based out in . It is known for research contribution in the topics: Computer science & Sliding mode control. The organization has 4264 authors who have published 3492 publications receiving 19371 citations. The organization is also known as: COEP.

Novel, low cost remotely operated smart irrigation system

Abstract: Agriculture plays very vital role in Indian economy. Near about 70% of Indian population directly depends on agriculture. The main aim of this paper is to provide new engineering technology in an agricultural area which enhances farmers life and Indian economy. Irrigation i.e. well-timed and ample amount of water supply is necessary for agriculture to increase its productivity. This paper develops a small embedded system device (ESD) which takes care of a whole irrigation process and makes farmers life easier. The PIC18F4550 microcontroller interfaced with GSM module works as a brain and several sensors like temperature, level and rain works as eyes of this ESD. The power detecting circuit and battery backup unit take this ESD to next level by informing presence of three phase power supply in the field. The farmer just needs to send predefined commands through SMS from her/his mobile phone to this ESD to carry out irrigation process effectively. If and only if eyes of the ESD sees all parameters are within a safe range, the PIC18F4550 starts irrigation process by starting the irrigation pump. The farmer gets time to time feedback from ESD through SMS about the action that has taken place by PIC18F4550. The GSM module allows farmers to operate and monitor a remotely placed irrigation pump from anywhere far from their field. The free SMS facilities provided to farmers makes it more cost effective. In this way, this new engineering technology makes farmers life easier by providing remotely operated, more efficient and cost effective irrigation system.

Effective thermal conductivity of polymer composites: a review of analytical methods

Abstract: Polymer composites are widely used in different areas such as the aircraft industry, automotive industry, electronic industry and packaging industry etc. Polymer composites should have various phys...

Image Retrieval Using Low Level and Local Features Contents: A Comprehensive Review

Abstract: Billions of multimedia data files are getting created and shared on the web, mainly social media websites. The explosive increase in multimedia data, especially images and videos, has created an issue of searching and retrieving the relevant data from the archive collection. In the last few decades, the complexity of the image data has increased exponentially. Text-based image retrieval techniques do not meet the needs of the users due to the difference between image contents and text annotations associated with an image. Various methods have been proposed in recent years to tackle the problem of the semantic gap and retrieve images similar to the query specified by the user. Image retrieval based on image contents has attracted many researchers as it uses the visual content of the image such as color, texture, and shape feature. The low-level image features represent the image contents as feature vectors. The query image feature vector is compared with the dataset images feature vectors to retrieve similar images. The main aim of this article is to appraise the various image retrieval methods based on feature extraction, description, and matching content that has been presented in the last 10–15 years based on low-level feature contents and local features and proposes a promising future research direction for researchers.

Design of area and delay efficient Vedic multiplier using Carry Select Adder

Abstract: In this paper, Vedic multiplier is designed using area-efficient Carry Select Adder (CSLA). As the multiplication is the process of subsequent addition, adder is important block in implementation of multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead of simple Ripple Carry Adder (RCA). Carry select adder is known to be one of the fastest adder structures. Here Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. The goal of this paper is to design Vedic multiplier based on crosswise and vertical algorithms using area-efficient CSLA. Conventional CSLA designs like Binary to Excess one Converter (BEC) based CSLA and Modified CSLA (MCSLA) are compared with proposed CSLA design to prove its efficiency. It shows improved performance in terms of area. This renovated CSLA is used to design proposed Vedic multiplier. It has 6% less area than Vedic multiplier using MCSLA and 16% less area than Vedic multiplier using BEC-based CSLA. Proposed design is also compared with the Booth multiplier. Proposed multiplier showed more excellent results than Booth multiplier.

Novel integrated development environment for implementing PLC on FPGA by converting ladder diagram to synthesizable VHDL code

Abstract: Programmable logic controllers (PLCs) are the universally accepted automation components in industrial control. IEC61131–3 standard was developed to unify textual and graphical ways of describing the control specification for PLCs; ladder diagram being one such control specifications. However, PLCs available in the market as on today are vendor specific and replacement of PLC of one vendor in a process equipment by PLC of another vendor is not possible due to lack of standardization among EDA tools from PLC vendors. Secondly, heart of PLCs is a sequential processor which cannot execute parallel rungs of ladder diagram concurrently. Perhaps this aspect did not pose any problem so far due to large response times associated with industrial processes. However with introduction of high speed MEMS sensors along with increased control complexity, the need for high speed PLCs has been spelt out. Further, the safety features of control system are now expected to be integral part of ladder control specification. Field Programmable Gate Arrays (FPGAs) have better portability support, ability to support implementation of concurrent logic and security aspects. They have been mentioned in the literature as prospective programmable devices to implement control logic of PLCs. However, utilization of FPGAs for implementing control specification demands development of integrated environment to convert ladder logic as per IEC61131–3 to HDL. This HDL specification further can be ported to any of the standard FPGA development environments. It is seen through literature that not enough efforts have been focused on developing such integrated environment. This paper focuses on the details of such environment being developed by authors to convert IEC-61131–3 control specification standard to VHDL for direct synthesis.