Journal ArticleDOI
A 15–22 Gbps Serial Link in 28 nm CMOS With Direct DFE
Vishnu Balan,Olakanmi Oluwole,Gregory Kodani,Charlie Zhong,Ratnakar Dadi,Arif Al Amin,Ahmed Ragab,M.-J. Edward Lee +7 more
TLDR
A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented and can be configured either as a pre-cursor or post- cursor 2-tap FIR filter.Abstract:
A half-duplex serial link design that is capable of 22 Gbps operation over PCB channels with up to 20 dB of loss is presented. A current-mode transmitter can be configured either as a pre-cursor or post-cursor 2-tap FIR filter. The receiver consists of a trans-admittance-trans-impedance single-stage linear equalizer that can provide 10 dB of high-frequency gain without the use of peaking inductors. The CTLE is followed by an half-rate 2-tap decision feedback equalizer with direct feedback. To mitigate long-tail intersymbol interference in a power-efficient manner, a third DFE tap employs a single-pole IIR filter. A 15-22 GHz LC-PLL provides quadrature clocks to a 16-lane macro. The 16-lane macro occupies 1.66 mm × 1.6 mm in a 28 nm CMOS process and is packaged in a 45 mm × 45 mm flip-chip MCM module. The link operates from two power supplies at 1.35 V and 0.9 V with a BER and a power efficiency of 6.5 mW/Gbps at 20 Gbps.read more
Citations
More filters
Journal ArticleDOI
A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor
TL;DR: A 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) that accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller.
Journal ArticleDOI
A 3.8 mW/Gbps Quad-Channel 8.5–13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS
Namik Kocaman,Tamer Ali,Lakshmi Rao,Ullas Singh,Mohammed Abdul-Latif,Yang Liu,Amr Amin Hafez,Henry Park,Anand Vasani,Zhi Huang,Arvindh Iyer,Bo Zhang,Afshin Momtaz +12 more
TL;DR: This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology and represents the lowest reported power in its class to date.
Proceedings ArticleDOI
A Case for Packageless Processors
TL;DR: It is shown that Si-IF-based packageless processors outperform their packaged counterparts by up to 58%, 136% (103% average), and 295% (80% average) due to increased memory bandwidth, increased allowable TDP, and reduced area respectively.
Proceedings ArticleDOI
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers
TL;DR: The proposed transmitter features feed-forward equalization with 8 taps, whose strength is programmable with 16 discretization steps, optimizing the transmitter adaptability with reduced area and achieves a remarkably low 2.25 pJ/bit total power consumption.
Journal ArticleDOI
A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces
Davide Menin,Alessio De Pra,Andrea Bandiziol,Werner Grollitsch,Roberto Nonis,Pierpaolo Palestri +5 more
TL;DR: A novel approach to simulate the convergence and the performance of high-speed serial interfaces with adaptive equalization that uses as input the pulse response of the channel that is then modified by adaptive techniques implementing feed-forward, decision-feedback, and linear-continuous time equalization.
References
More filters
Proceedings ArticleDOI
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
TL;DR: A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage, which enables fast operation over a wide common-mode and supply voltage range as discussed by the authors.
Journal ArticleDOI
Improved sense-amplifier-based flip-flop: design and measurements
Borivoje Nikolic,Vojin G. Oklobdzija,Vladimir Stojanovic,Wenyan Jia,James Kar Shing Chiu,M. Ming-Tak Leung +5 more
TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.
Journal ArticleDOI
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
John W. Poulton,Robert E. Palmer,Andrew M. Fuller,Trey Greer,John Eyles,William J. Dally,Mark Horowitz +6 more
TL;DR: A 6.25-Gb/s 14-mW transceiver in 90-nm CMOS for chip-to-chip applications with a number of features for reducing power consumption, including a shared LC-PLL clock multiplier, an inductor-loaded resonant clock distribution network, a low- and programmable-swing voltage-mode transmitter, and software-controlled clock and data recovery.
Proceedings ArticleDOI
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
John F. Bulzacchelli,Christian Menolfi,Troy J. Beukema,Daniel W. Storaska,Juergen Hertle,David R. Hanson,Ping-Hsuan Hsieh,Sergey V. Rylov,D. Furrer,Daniele Gardellini,Andrea Prati,Thomas Morf,V. Sharma,R. Kelkar,Herschel A. Ainspan,William R. Kelly,L. R. Chieco,G. A. Ritter,J. A. Sorice,Jon D. Garlett,Robert Callan,Matthias Brandli,P. Buchmann,Marcel Kossel,Thomas Toifl,Daniel J. Friedman +25 more
TL;DR: This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE.
Journal ArticleDOI
A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS
Ganesh Balamurugan,Joseph T. Kennedy,Gaurab Banerjee,James E. Jaussi,Mozhgan Mansuri,Frank O'Mahony,Bryan K. Casper,R. Mooney +7 more
TL;DR: A scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps is presented.