242 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 2, FEBRUARY 2011
An Efficient Gate Library
for Ambipolar CNTFET Logic
M. Haykel Ben-Jamaa, Member, IEEE, Kartik Mohanram, Member, IEEE,
and Giovanni De Micheli, Fellow, IEEE
Abstract—Recently, several emerging technologies have been
reported as potential candidates for controllable ambipolar
devices. Controllable ambipolarity is a desirable property that
enables the on-line configurability of n-type and p-type device
polarity. In this paper, we introduce a new design methodology
for logic gates based on controllable ambipolar devices, with
an emphasis on carbon nanotubes as the candidate technol-
ogy. Our technique results in ambipolar gates with a higher
expressive power than conventional complementary metal-oxide-
semiconductor (CMOS) libraries. We propose a library of static
ambipolar carbon nanotube field effect transistor (CNTFET)
gates based on generalized
NOR-NAND-AOI-OAI primitives,
which efficiently implements XOR-based functions. Technology
mapping of several multi-level logic benchmarks that extensively
use the XOR function, including multipliers, adders, and linear
circuits, with ambipolar CNTFET logic gates indicates that on
average, it is possible to reduce the number of logic levels by
42%, the delay by 26%, and the power consumption by 32%,
resulting in a energy-delay-product (EDP) reduction of 59% over
the same circuits mapped with unipolar CNTFET logic gates.
Based on the projections in [1], where it is stated that defect-
free CNTFETs will provide a 5× performance improvement over
metal-oxide-semiconductor field effect transistors, the ambipolar
library provides a performance improvement of 7×, a 57%
reduction in power consumption, and a 20× improvement in
EDP over the CMOS library.
Index Terms—Ambipolar carbon nanotubes, ambipolar silicon
nanowires, ambipolarity, logic design, logic synthesis.
I. Introduction
T
HE CONTINUOUS scaling of metal-oxide-semiconduc-
tor field effect transistors (MOSFETs) led to the consid-
eration of devices with intrinsic channel and Schottky barrier
(SB) contacts. Such transistors are ambipolar, i.e., they behave
either as n-type or p-type devices, depending on the bias
Manuscript received December 6, 2009; revised April 20, 2010, July 25,
2010, and August 20, 2010; accepted August 24, 2010. Date of current
version January 19, 2011. This work was supported in part by the Swiss NSF,
under Grants 20021-109450/1 and ERC-2009-AdG-246810, by the U.S. NSF,
under Grant CCF-0916636, and by the ERC, under Senior Grant NANOSYS
ERC-2009-AdG-246810. This paper was recommended by Associate Editor
I. Markov.
M. H. Ben-Jamaa is with Commissariat
`
a l’Energie Atomique et aux Ener-
gies Alternatives, Grenoble 38000, France (e-mail: haykel.ben-jamaa@cea.fr).
K. Mohanram is with the Departments of Electrical and Computer Engi-
neering and Computer Science, Rice University, Houston, TX 77005 USA.
G. D. Micheli is with
´
Ecole Polytechnique F
´
ed
´
erale de Lausanne, Lausanne
1015, Switzerland.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAD.2010.2085250
conditions. A back gate can be used in order to control the
device polarity. It has been shown recently that the unique
property of in-field polarity control can yield denser and faster
design of reconfigurable logic circuits [2], [3].
Different technologies represent potential candidates for
ambipolar logic, including silicon nanowire field effect tran-
sistors [4], carbon nanotube field effect transistors (CNT-
FETs) [5], and graphene nanoribbons [6]. Devices fabricated
in any of these technologies have two gates, controlling both
current conduction and device polarity as illustrated in Fig. 1.
The ultimate goal of design using these devices is to leverage
their controllable ambipolarity at the logic level, which yields a
very compact realization of the XOR function, and its potential
embedding into more complex logic gates.
It has been suggested in previous work that embedding
the XOR operation into other gates results in generalized
logic gates [2], i.e., reconfigurable gates whose input polarities
can be set in the field. This results in a higher expressive
power, i.e., the potential to implement more complex functions
using fewer physical resources. In [2], generalized
NOR (GNOR)
gates, combining
NOR and XOR operations, were described.
In [3], the investigation of the potentials of ambipolar logic
gates was restricted to the characterization of a single universal
reconfigurable 8-function gate. The intrinsic reason for the
high expressive power lies in the presence of an inverting
device behavior (as, for example, a p-device in the pull-
down network or vice versa) enabling the realization of binate
functions in single logic gates.
However, prior work with ambipolar devices has only
demonstrated dynamic logic, where function monotonicity
requirements limit the potential of multi-level logic implemen-
tations. Furthermore, multi-level logic synthesis that leverages
the high expressive power of ambipolar devices has not been
investigated in the literature. Unlike ambipolar logic gates that
implement XOR operations in a compact form, traditional
libraries provide the universal NAND,
NOR, and compound
AOI/OAI gates, but fail to efficiently implement circuits that
contain one or more binate operations such as the XOR. This
makes them inefficient for circuits such as n-bit adders and
parity functions that are efficiently implemented using XOR
gates [8].
This paper exploits the unique in-field controllability of the
device polarity of ambipolar transistors. It deals with design
aspects of ambipolar gates, and it is applicable to SiNW,
CNT, and graphene technologies. Whereas this paper proposes
0278-0070/$26.00
c
2011 IEEE
BEN-JAMAA et al.: AN EFFICIENT GATE LIBRARY FOR AMBIPOLAR CNTFET LOGIC 243
Fig. 1. Double gate ambipolar transistor. (a) Layout. (b) Symbol. (c) Con-
figuration as n-type and p-type.
a general methodology, it specializes on SB CNTFETs as
an example of the investigated devices in order to design
a family of full-swing static logic gates in a transmission
gate configuration. The contributions of this paper can be
summarized as follows.
1) Based on generalized
NOR/NAND/AOI/OAI primitives
that embed XORs, the family is used to build a tech-
nology library with a significantly higher expressive
power than conventional complementary metal-oxide-
semiconductor (CMOS) libraries, which targets the de-
sign of circuits that extensively use the XOR function.
2) This paper extends our approach in [9] by enhancing the
library characterization in terms of area and delay with
a power model.
In this paper, we demonstrate that logic gates with no
more than three ambipolar devices each in the pull-up (PU)
and pull-down (PD) networks, respectively, can implement 46
different functions, which can be extended to 158 different
derived functions (Section III). This is in contrast to only seven
functions with CMOS logic using the same topology. This core
family of static logic gates can be extended to a pseudo-logic
family with transmission gates in the PD network, a static
logic family with pass transistors in the PU and PD networks,
and a pseudo-logic family based only on pass transistors in
the PD network. Technology mapping of several multi-level
logic benchmarks, including multipliers, adders, and linear
circuits, using ambipolar CNTFET logic gates indicates that
on average, it is possible to reduce the number of logic levels
by 42%, the delay by 26%, and the power consumption by
32%, resulting in an energy-delay-product (EDP) reduction of
59% over the same circuits mapped with unipolar CNTFET
logic gates. Based on the prediction given in [1], stating
that defect-free CNTFETs have a 5× better performance than
MOSFETs, the performance improvement over the CMOS
mapping is 7×, while the power consumption is reduced by
57% and the EDP by 20×. The proposed design approach in
this paper can be generalized to other transistor technologies
as long as the device ambipolarity can be controlled after
manufacturing. However, the benefits will depend on the
underlying technology.
This paper is organized as follows. Section II provides
a background and surveys technologies and circuit design
approaches based on ambipolar devices. Section III introduces
the novel design approach based on transmission-gate static
logic gates with ambipolar CNTFETs. Then, Section IV ex-
tends this static family to pseudo-logic using either transmis-
sion gates or pass-transistors. Section V is dedicated to the
characterization of the designed libraries in terms of delay and
weighted device count; then large logic circuits are synthesized
and mapped using those gates in Section VI. In Section VII,
a model to estimate the power consumption of the static
transmission gates is introduced. The power consumption
of the proposed library is estimated in Section VIII and
compared to CMOS gates. Then, the power consumption of
the previously synthesized and mapped circuits is estimated
in Section IX. Section X summarizes the comparison between
unipolar and ambipolar design and discusses future directions
for further assessment of the ambipolar design methodology.
In Section XI, we conclude this paper.
II. Background and Motivation
This section surveys previous works related to physics
and technology of ambipolar CNTFETs, which illustrates
the ambipolar technologies underlying our proposed design
methodology. It also summarizes previous approaches to lever-
age the controllable ambipolarity at the circuit level.
A. Ambipolar Technologies
Several technologies represent potential platforms for the
design of ambipolar logic gates. Recently, ambipolar behavior
has been reported on silicon nanowire field effect transistors
(SiNWFETs) [10]. Moreover, GNRFETs have an ambipolar
behavior when their width is confined to less than 10 nm [6],
[11]. Ambipolar behavior has also been reported in CNT-
FETs [12]. In this paper, we focus on CNT technology
to illustrate the general design methodology for ambipolar
gates, since CNTFETs have been shown to deliver higher
performance than other technologies [1].
When intrinsic CNTs are used as the channel material
in CNTFETs, then the fabricated devices have a Schottky
barrier at the contacts and exhibit ambipolar behavior, i.e.,
they conduct both electrons and holes, showing a superpo-
sition of n-type and p-type behaviors. The Schottky barrier
thickness is modulated by the fringing gate field at the CNT-
to-metal contact, allowing the polarity of the device to be
set electrically [12]. The ability to control CNTFET polarity
(p-type or n-type) in the field by controlling the fringing
gate field suggests the innovation of using a second gate,
termed the polarity gate throughout this paper, to control the
electrical field at the CNT-to-metal junction and to set the
device polarity [12]. Thus, CNTFETs can be used to realize
in-field programmable ambipolar devices, i.e., devices whose
p-type or n-type behavior can be programmed in the field using
the polarity gate.
The physics of the considered double-gate device is illus-
trated using the band diagram in Fig. 2. The fields A and B are
integral to the channel, i.e., the CNT, and are controlled by the
conventional and the polarity gate, respectively. By setting the
polarity gate to a positive value (V
PG
= V
+
), the band diagram
becomes thin and transparent for electrons (e
−
), which can
tunnel through the SB, and it remains thick for holes (h
+
),
which are then stopped by the SB. A resulting electron current
can flow along the channel, as long as the gate voltage is
positive (V
G
> 0), thus making the device operate as a n-type
transistor. The opposite happens when the polarity gate is set to
244 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 2, FEBRUARY 2011
Fig. 2. Band diagram of a double-gate ambipolar CNTFET: the fields A
and B are controlled by the conventional and the polarity gate, respectively.
The band diagram of the n-type and p-type behaviors of the same device
under different polarity gate biases are illustrated on the left and right sides,
respectively.
a negative value (V
PG
= V
−
). Then the SB becomes transparent
for holes and the device operates as a p-type transistor.
B. Operation of Ambipolar Devices
A technique to manufacture in-field programmable CNT-
FETs based on double-gate devices has been proposed in [12].
The device layout, including a bottom gate that is different
from the substrate has been introduced in Fig. 1(a); and its
symbol used in this paper has been shown in Fig. 1(b). The
device has two gates G and PG. The gate G turns the device
on or off, as the regular gate of a MOSFET, while the polarity
gate (PG) controls the type of polarity setting to p-type or n-
type. If a large positive voltage is applied at PG, the device
behaves as a n-type transistor, while a large negative voltage
applied at PG would set the polarity to p-type. For simplicity
with respect to logic design with ambipolar devices, which
will be introduced in the following sections, the logic 0 at PG
is defined as the required positive voltage to set the n-type
polarity, while the logic 1 is defined as the required negative
voltage to set the p-type polarity [Fig. 1(c)]. Note that logic
0 and 1 may correspond to different voltage levels at G and
PG, and we discuss this in greater detail in Section X.
We assume in this paper that the technological aspects
challenging the operation of CNTFETs, such as variability
and lack of control of the chirality, diameter, and placement
of the fabricated CNTs, will be addressed as the technology
matures. Our focus is on the ideal operation of the ambipolar
CNTFETs. Our proposed methodology can be generalized
to other technologies, as long as the ambipolarity can be
controlled in the field.
C. Previous Design Approaches with Ambipolar Devices
The novel in-field programmability of CNTFETs was inves-
tigated in previous works in order to extend the possibilities
offered by MOSFETs. In [3] and [13], a compact in-field
reconfigurable logic gate that maps eight different logic func-
tions of two inputs using only seven CNTFETs in dynamic
logic was presented. A full adder and an arithmetic logic
unit (ALU) were designed using this reconfigurable logic gate
Fig. 3. Dynamic GNOR gate: Y = (A ⊕B)+(C ⊕D) [2].
in [14]. Similarly, another reconfigurable 6-function logic gate
including XOR and
XNOR was designed in [15] and used in a
matrix-based regular architecture to map logic circuits.
In [2], the design of a
GNOR gate was proposed as the
core building block to realize in-field PLAs. It has a compact
design and a high expressive power by combining both
NOR
and XOR operations in the output function. For example,
the dynamic
GNOR gate in Fig. 3 implements the function
Y =
(A ⊕B)+(C ⊕D) with a relatively small number of
transistors, and makes use of the signals B and D as free
variables. The transistors T
PC
and T
EV
execute the usual
“precharge” and “evaluate” operations in dynamic logic.
These
GNOR-based PLAs offer the opportunity of mapping
logic functions into the compact and fast Whirlpool PLAs [16].
Another option is the realization of AND-XOR PLAs. It has
been shown [17] that such AND-XOR planes efficiently map
specific families of logic functions, including adders. In [17],
the design using XOR function has been investigated in an
independent way on the underlying technology. Some func-
tions, such as parity functions, can be efficiently implemented
in circuits using XOR gates.
III. Ambipolar Static Transmission-Gate Logic
Previous approaches using ambipolar devices in logic design
are based on dynamic logic. However, dynamic logic has two
major weaknesses when combined with ambipolar devices.
First, it is vulnerable to internal signal races. Second, in the
example depicted in Fig. 3, if both signals B and D are equal
to 1, then the PD network will be formed exclusively by
p-type devices. This can pull down the output to V
SS
+|V
Tp
| at
most. The output does not provide full swing, and worsens
further when stages are cascaded, seriously compromising
noise margins. Another disadvantage of dynamic logic is that
dynamic logic gates implement functions that tolerate only
monotonic transitions at the outputs.
We can possibly think of compensating the cascading issue
by adding a restoration stage (inverter or a buffer) at the
function output to restore the output swing. However, this
represents a certain area and delay overhead to the logic
gates. In addition, this option does not address the issue
of monotonicity of the implemented functions. Similar to
CMOS, it is possible extend the design of ambipolar gates
to complementary static logic by inserting a PU network that
represents the complement of the PD network. Whereas this
solves the problem of monotonicity, the potential presence of
n-type (p-type) CNTFET(s) in the PU (PD) network may still
BEN-JAMAA et al.: AN EFFICIENT GATE LIBRARY FOR AMBIPOLAR CNTFET LOGIC 245
Fig. 4. CNTFET transmission gate: any passing configuration (A ⊕B =1)
prevents signal degradation.
Fig. 5. Circuit implementation of ambipolar CNTFET logic gates with no
more than two transmission gates or transistors in the PU/PD networks.
result in a degradation of the output signal. In fact, an n-type
device in the PU network passes V
DD
− V
Tn
at most, and a
p-type device in the PD network passes V
SS
+ |V
Tp
| at least,
causing signal degradation in both cases.
In order to obtain a static design and guarantee full voltage
swing in all configurations, we replace each CNTFET whose
polarity is to be set during operation by a transmission gate
formed by two CNTFETs controlled (at both the regular
gate and the polarity gate) by complementary signals. In
a transmission gate, both n-type and p-type devices are in
parallel to ensure that one of the two transistors restores the
signal level in all cases (Fig. 4).
We combine this approach with the extension of the
GNOR
gates to generalized NAND and generalized AOI and OAI
(GAOI and GOAI) configurations, by considering series-
parallel combinations of transmission gates and transistors in
the PU/PD paths. Fig. 5 illustrates the circuit implementation
of all gates that can be obtained using no more than two
transmission gates or transistors in series/parallel in the PU/PD
networks. The derivation of transistor aspect ratios (W/L),
indicated in the figure, will be explained in Section V.
With no more than three transmission gates and transistors
in the PU or PD networks, with a maximum of three inputs
(applied to the gates) and three control inputs (applied to
the polarity gates), we obtain 46 different basic logic gates
listed in Table II. Even though every transmission gate has
TABLE I
Number of Gates and Average Transistor Count for Different
Designs and Gate Structures
Conventional Design
Generalized Design
Structure
Gates Trans. Gates (no sw.) Gates (sw.) Trans.
2 3 3.3
10 23 5.8
3
7 4.9 46
158 9.1
The structure of a gate designates the maximum number of
pass-transistors or transmission gates it has in its PU or PD network.
two transistors, a topologically uniform comparison between
CNTFET-based and CMOS-based gates suggests that we con-
sider CMOS gates with three inputs at most, instead of six.
Then, with the same constraints and topology, we obtain only 7
CMOS-based logic gates (F00, F02, F03, F10, F11, F12, and
F13), highlighting the higher expressive power of the proposed
transmission-gate-based static logic family.
In this design approach, whenever the function U ⊕ V is
implemented with transmission gate CNTFET, both polarities
of U and V are needed, as illustrated in Fig. 5. By swapping
the order in which the signals with different polarities are
applied to the transmission gates, it is possible to implement
U ⊕ V , U ⊕
V and U ⊕ V . Since U ⊕ V ≡
U ⊕ V and
U ⊕ V ≡ U ⊕
V , it is possible to implement one more
function by utilizing the same resources. For example, the
circuit implementing F07:
(A ⊕B) ·(A ⊕C) also implements
(A ⊕B) ·(A ⊕C), (A ⊕ B) ·(A ⊕C), and (A ⊕B) ·(
A ⊕C).
These four functions can be derived from F07 just by swapping
the inputs A
A, or equivalently, by swapping B
B and/or
C
C accordingly. However, from the circuit implementation
point of view,
(A ⊕B) ·(A ⊕C) and (A ⊕B) ·(A ⊕C) are
equivalent, given that they are derived from the same logic gate
by swapping signals B and C. Then, the number of distinct
gates that can be derived from the function of the gate F07
is 3 (instead of 4). The number of distinct gates obtained for
every function by swapping polarities is included in Table II,
and it sums up to 158 gates in total.
There are two types of cells in this generalized family: those
that are formed exclusively by pass-transistors and those that
contain transmission gates. The first subset of the cells covers
the gates F00, F02, F03, F10, F11, F12, and F13, which can
be fabricated in any unipolar technology, for instance with
MOSFETs or MOSFET-like CNTFETs. We refer to this subset
in this paper as the conventional gates. The second subset of
logic cells embed one or more XOR functions in an efficient
manner. They cannot be fabricated with a unipolar technology,
and they are therefore referred to as non-conventional gates.
We define the structure of a logic gate as follows: primary,
secondary, and ternary gates as those having exactly one, two,
and three transmission-gate(s) and/or pass-transistor(s) in their
PU and PD networks, respectively.
The existence of derived gates, generated by swapping the
signals and their complements, offers a high flexibility in
designing the generalized gates, which is more important for
larger gate structures. Table I summarizes the number of logic
gates obtained for different gate structures for both the general-
ized and conventional families. We considered both cases with
and without signal polarity swapping. The results in Table I
246 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 2, FEBRUARY 2011
show that the generalized family with a ternary structure has
22× more gates than its conventional counterpart when the
derived gates through polarity swapping are taken into account.
This fact confirms the high expressive power of the designed
gates. The average number of transistors is also provided and
it is about 75 to 85% larger for the generalized implementation
in comparison to the conventional implementation.
IV. Alternate Ambipolar Logic Families
If transistor count and gate area are more critical than power
consumption, then a pseudo-logic implementation of the same
set of logic gates listed in Table II is preferred to the previously
introduced transmission-gate static logic implementation. As
for standard CMOS gate, pseudo-logic can be derived from
static logic by replacing the PU network by a PU CNTFET
biased as a p-type device. The PU CNTFET is weaker than the
PD devices in order to allow the output signal to fall within
the tolerated margin. Fig. 6 (bottom-left quadrant) depicts
the pseudo-logic implementation of F05 combined with the
transmission-gate approach. The rest of the gates summarized
in Table II can be designed in transmission gate pseudo-logic
in a similar way.
An alternative approach to reduce the transistor count is
to replace all transmission-gates by pass-transistors. However,
this requires that ambipolar CNTFETs that are electrically
configured as n-type or p-type be located in the PU or PD
network, respectively. They therefore conduct with a high
resistance and cause the output level to be degraded. In
order to restore the full swing of the output, a restoration
stage (buffer or inverter) is inserted. This requires two more
transistors and an additional gate delay, which will be assessed
in Section V. Fig. 6 depicts the pass-transistor implementations
of F05 as an example in static (top-right quadrant) and pseudo-
logic (bottom-right quadrant), respectively. The other gates
summarized in Table II can be designed in pass-transistor
(static and pseudo) logic in a similar way.
V. Area and Delay of Logic Gates
In order to design libraries of ambipolar CNTFETs, we first
validated the correctness of our design approach by simulating
the designed gates. Ambipolar CNTs are an emerging technol-
ogy, and simulating ambipolar CNTFET gates is not an easy
task, given the fact that at present, there is no general and
SPICE-compatible model for SB CNTFETs (i.e., ambipolar
CNTFETs). The SB CNTFET model presented in [18] is
restricted to a specific CNT chirality, is not SPICE-compatible,
and does not allow for the in-field controllability of the
ambipolarity. On the other hand, the MOSFET-like CNTFET
model released in [19] is SPICE-compatible and offers more
freedom with respect to the choice of the CNT parameters,
such as CNT count and chirality. However, it does not allow
for in-field control of device polarity.
Ambipolar behavior can be emulated in a SPICE-
environment by using the Stanford MOSFET-like CNTFET
model. A method has been presented in [3]: every ambipo-
lar CNTFET can be replaced by two parallel MOSFET-like
TABLE II
Ambipolar CNTFET Logic Gates With No More Than Three
Series Transmission-Gates or Transistors in Each PU/PD
Network
Gate Basic Function
Derived Functions
F00 A 1
F01
A ⊕ B 2
F02 A + B 1
F03
A · B
1
F04 (A ⊕ B)+C
2
F05 (A ⊕ B) · C
2
F06
(A ⊕ B)+(A ⊕C)
3
F07
(A ⊕ B) ·(A ⊕ C) 3
F08
(A ⊕ B)+(C ⊕ D) 3
F09
(A ⊕ B) ·(C ⊕D) 3
F10
A + B + C 1
F11 (A + B) ·C
1
F12 A +(B · C)
1
F13
A · B · C 1
F14 (A ⊕ D)+B + C 2
F15 (A ⊕ D)+(B ⊕D)+C
3
F16 (A ⊕ D)+(B ⊕D)+(C ⊕D)
4
F17 ((A ⊕ D)+B) · C 2
F18 ((A ⊕ D)+(B ⊕D)) ·C
3
F19
((A ⊕ D)+B) · (C ⊕ D) 4
F20
((A ⊕ D)+(B ⊕D)) ·(C ⊕ D)
6
F21 (A + B) ·(C ⊕ D) 2
F22 (A ⊕ D)+(B ·C) 2
F23
A +(B ⊕ D) ·C 2
F24
(A ⊕ D)+(B ⊕D) ·C 4
F25 A +(B ⊕ D) ·(C ⊕ D) 3
F26 (A ⊕ D)+((B ⊕ D) ·(C ⊕D))
6
F27
(A ⊕ D) ·B · C 2
F28 (A ⊕ D) ·(B ⊕ D) ·C 3
F29 (A ⊕ D) ·(B ⊕ D) ·(C ⊕ D) 4
F30
(A ⊕ D)+(B ⊕E)+C 3
F31 (A ⊕ D)+(B ⊕D)+(C ⊕E) 8
F32 ((A ⊕ D)+(B ⊕E)) ·C
3
F33
((A ⊕ D)+B) · (C ⊕ E) 4
F34 ((A ⊕ D)+(B ⊕D)) ·(C ⊕ E) 6
F35 ((A ⊕ D)+(B ⊕E)) ·(C ⊕ D) 8
F36
(A ⊕ D)+((B ⊕ E) ·C) 4
F37 A +((B ⊕D) ·(C ⊕E)) 3
F38 (A ⊕ D)+((B ⊕ E) ·(C ⊕E))
6
F39 (A ⊕ D)+((B ⊕ E) ·(C ⊕D)) 8
F40 (A ⊕ D) ·(B ⊕ E) ·C
3
F41
(A ⊕ D) ·(B ⊕ D) ·(C ⊕ E) 6
F42 (A ⊕ D)+(B ⊕E)+(C ⊕F ) 4
F43 ((A ⊕ D)+(B ⊕E)) ·(C ⊕ F) 6
F44
(A ⊕ D)+((B ⊕ E) ·(C ⊕F )) 6
F45 (A ⊕ D) ·(B ⊕ E) ·(C ⊕ F ) 4
Total 158
CNTFETs with opposite polarities as depicted in Fig. 7. Note
that this technique only emulates the ambipolar behavior, and
it does not allow for any control of the ambipolarity, which
has to be realized manually in the HSPICE simulations. We
followed this approach to emulate ambipolar CNTFETs by
using the SPICE-compatible Stanford model for MOSFET-
like CNTFETs [19]. Then, in order to control the polarity, we
![Fig. 3. Dynamic GNOR gate: Y = (A⊕ B) + (C ⊕D) [2].](/figures/fig-3-dynamic-gnor-gate-y-a-b-c-d-2-3vcfcten.webp)
