Seo, J., Lee, J. and Shin, M. (2014) Analysis of drain-induced barrier rising
in short-channel negative-capacitance FETs and Its applications. IEEE
Transactions on Electron Devices, 64(4), pp. 1793-1798.
(doi:10.1109/TED.2017.2658673)
This is the author’s final accepted version.
There may be differences between this version and the published version.
You are advised to consult the publisher’s version if you wish to cite from
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1
Analysis of Drain-Induced Barrier Rising in
Short-Channel Negative Capacitance FETs and Its
Applications
Junbeom Seo, Jaehyun Lee, and Mincheol Shin
Abstract—We investigate the performance of hysteresis-
free short-channel negative-capacitance field-effect transistors
(NCFETs) by combining quantum mechanical calculations with
the Landau-Khalatnikov equation. When the subthreshold swing
(SS) becomes smaller than 60 mV/dec, a negative value of drain-
induced barrier lowering (DIBL) is obtained. This behavior,
drain-induced barrier rising (DIBR), causes negative differential
resistance (NDR) in the output characteristics of NCFETs.
We also examine the performance of an inverter composed of
hysteresis-free NCFETs to assess the effects of DIBR at the
circuit level. Contrary to our expectation, although hysteresis-
free NCFETs are used, hysteresis behavior is observed in the
transfer properties of the inverter. Furthermore, it is expected
that the NCFET inverter with hysteresis behavior can be used
as a Schmitt trigger inverter.
Index Terms—Subthreshold swing, ferroelectric, negative ca-
pacitance FET, hysteresis behavior, drain-induced barrier lower-
ing, Schmitt trigger inverter
I. INTRODUCTION
A
S conventional metal-oxide-semiconductor field-effect-
transistors (MOSFETs) are reduced to a nanometer scale,
the subthreshold swing (SS) reaches the fundamental thermal
limit of 60 mV/dec [1]. It is well-known that this limitation
is an obstacle to achieving high-performance and low-power
consumption devices. To solve this issue, new device concepts,
such as impact ionization MOS (I-MOS) [2] and tunneling
FETs (TFETs) [3] have been suggested. Despite their out-
standing features, I-MOS suffers from reliability issues and
is not suitable for low-power consumption devices because of
their high applied voltages. In the case of TFETs, ON-state
current (I
ON
) is restricted due to tunneling probability, even
though sub-60 mV/dec switching behavior occurs [3]-[6].
In recent years, negative capacitance FETs (NCFETs), pro-
posed by Salahuddin et al. [7], have received much attention
as a new type of steep switching device. NCFETs are capable
of achieving steep SS and high I
ON
by amplification of the
gate voltage (V
GS
) through the ferroelectric material. Unlike I-
MOS and TFETs, the I
ON
of NCFETs strongly depends on the
thermionic currents. According to recent experimental studies
on NCFETs, they have successfully achieved very steep SS
values of 18 and 11.3 mV/dec as well as a high ON/OFF
current ratio with low drain volgate (V
DS
) [8]-[10].
(Corresponding author : Mincheol Shin.)
The authors are with the School of Electrical Engineering, Korea Advanced
Institute of Science and Technology, Daejeon 34141, South Korea (e-mail:
jbseo@kaist.ac.kr; jaehyun.lee@kaist.ac.kr; mshin@kaist.ac.kr).
Fig. 1. (a) Schematic structure of the UTB NCFET and (b) a series of
ferroelectric (C
F E
), dielectric (C
ox
), and semiconductor capacitors (C
s
).
The gate capacitance (C
G
) is modeled as a series capacitance of C
F E
and
C
ox
.
There has been growing interest in the evaluation and
optimization of NCFETs. Kobayashi et al. [11] suggested
exploiting the ferroelectric properties to design low-power
NCFETs. The dependences of NCFET performances on fer-
roelectric thickness (T
F E
) have been studied extensively [12]-
[16]. Khan et al. [17] provided guidelines for parameters to
develop low-power NCFETs. Since NCFETs are based on
conventional MOSFETs, they may be vulnerable to short-
channel effects (SCEs). Recently, Li et al. [18] pointed out
the coupling effects between gate and drain on the device
performance of short-channel bulk NCFETs. Except for Li’s
work, SCEs on NCFETs have never been reported.
In this work, we investigated the performance of short-
channel NCFETs through quantum mechanical simulations
with the Landau-Khalatnikov (LK) equation. We especially
focused our attention on the SCEs associated with V
DS
and drain-induced barrier lowering (DIBL). Furthermore, we
explored the influence of SCEs on the inverter to verify the
viability of NCFETs at the circuit level.
The remainder of this paper is organized as follows. Section
II describes our simulation approach based on the LK theory
and quantum transport. In Section III, the basic properties of
NCFETs are presented focusing on the SCEs. We discuss
the characteristics of the NCFET inverter and propose a
new application in Section IV, followed by a summary and
conclusions in Section V.
2
Fig. 2. Flowchart of the NCFET simulation.
II. SIMULATION APPROACH
A schematic diagram of the ultra-thin body (UTB) double-
gate (DG) NCFETs simulated in this work is shown in Fig.
1(a). The key difference between the structure of NCFETs
and conventional MOSFETs is the presence of a ferroelectric
material in the gate stack. As in the case of recent experiments
[8][9], the ferroelectric and baseline MOSFET in our work
are supposed to be spatially separated, but connected by a
metal layer with the same contact area, which provides the
same gate charge density (Q
G
) to both the internal gate and
ferroelectric surfaces. The channel length (L
ch
) and T
F E
are
subject to variation, whereas the channel thickness (T
Si
) and
equivalent oxide thickness (EOT) are assumed to be 5 and 2
nm, respectively.
Fig. 1(b) describes the equivalent capacitance model. An
NCFET can be depicted with three capacitances, including
ferroelectric, dielectric, and semiconductor capacitors. The
total gate capacitance (C
G
) consists of a series combination
of oxide (C
ox
) and ferroelectric (C
F E
) capacitances. The
internal voltage (V
int
) indicates the voltage amplified by the
ferroelectric, and it acts as V
GS
in the conventional MOSFET.
The overall simulation procedure shown in Fig. 2 consists
of two parts: electronic calculation and ferroelectric capacitor
modeling.
First, we solve the non-equilibrium Greens function (NEGF)
and Poisson equation self-consistently in the ballistic transport
regime for the conventional MOSFET with the same dimen-
sions as those of NCFETs [19]. In the channel region, the
effective mass Hamiltonian and 6 bands k · p Hamiltonian for
n-type and p-type devices are used to describe the conduction
and valence bands, respectively. The effective masses are
calibrated from the sp
3
d
5
s
∗
tight-binding method [20]. The
Luttinger parameters are adjusted from the sp
3
s
∗
tight-binding
method [21]. From the self-consistent calculation, we obtain
Q
G
and drain current (I
D
) as a function of V
GS
.
Next, the ferroelectric capacitor is modeled as follows.
The LK equation [22][23] which describes the dynamics of
polarization in response to time is given as
ρ
dP
dt
+ ∇
~
P
U = 0, (1)
where ρ, P , and t are resistivity, polarization, and time, respec-
tively. Here, U represents the free energy of the ferroelectric
material and is defined by the Landau-Devonshire (LD) theory
[24] as
U = αP
2
+ βP
4
+ γP
6
−
~
E ·
~
P , (2)
where E is an external electric field and α, β, and γ are the
order parameters. In the case of the ferroelectric material, α
is always negative. In this work, the ferroelectric material is
assumed to be SrTiO
3
with the parameters of α = −6.5 × 10
7
m/F , β = 3.75 × 10
9
m
5
/F/C
2
, and γ = 0 m
9
/F/C
4
[25].
We note that the use of bulk order parameters in this work
may be justified considering the supposed spatial separation
between the ferroelectric and baseline MOSFET. However, in
an ultimate integration of ferroelectric into the gate stack, the
size of ferroelectric should affect the ferroelectricity [26]-[28]
and thus leads to different order parameters than the bulk ones.
We nevertheless believe that the overall trend as predicted from
the results of this work might not change in nature.
We assume that the ferroelectric is in steady-state polariza-
tion (dP/dt = 0). Substituting Eq. (2) into Eq. (1), the electric
field is given as
E = 2αP + 4βP
3
, (3)
which can be further derived as
V
int
= V
GS
− [2αP + 4βP
3
]T
F E
, (4)
where V
int
, V
GS
, and T
F E
are the internal voltage, gate
bias, and ferroelectric thickness, respectively. Since Q
G
can
be expressed as Q
G
= P +
0
E ≈ P because P of the
ferroelectric is larger than
0
E, Eq. (4) is approximated as
V
int
= V
GS
− [2αQ
G
+ 4βQ
3
G
]T
F E
. (5)
Finally, the drain current at a particular gate voltage
(V
NCF ET
GS
) in NCFETs, I
NCF ET
D
(V
NCF ET
GS
), is obtained
by looking up the drain current in the conventional
MOSFET which was precalculated in the previous step,
I
MOSF ET
D
(V
GS
), as follows:
I
NCF ET
D
(V
NCF ET
GS
) = I
MOSF ET
D
(V
GS
),
where V
GS
= V
int
(V
NCF ET
GS
) as given by Eq. (5).
III. CHARACTERISTICS OF NCFET
A. Dependence on T
F E
Fig. 3 presents the transfer characteristics of conventional
MOSFETs and NCFETs with L
ch
= 20 nm, respectively.
As T
F E
increases, I
ON
increases and SS decreases. For
instance, NCFETs with T
F E
= 270 nm provide larger I
ON
(12.9 mA/µm) and lower SS (43.5 mV/dec) than conventional
3
-0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
10
-6
10
-4
10
-2
10
0
10
2
(a)
0.03 0.06 0.09 0.12
-1
0
1
2
3
C
MOS
> |C
FE
|
C
MOS
|C
FE
|
270 nm
380 nm
Q
G
[ C /cm
2
]
Capacitance [pF/cm
2
]
V
GS
[V]
I
D
[m A/ m]
T
FE
= 0 nm
170 nm
270 nm
380 nm
60 mV/dec
Fig. 3. Transfer characteristics of the conventional MOSFET (T
F E
= 0 nm)
and NCFETs with T
F E
= 170, 270 and 380 nm. Inset shows Q
G
versus the
capacitance of NCFETs with T
F E
= 270 and 380 nm.
0 100 200 300 400
-400
-200
0
200
400
600
800
0 100 200 300 400
0
20
40
60
80
100
120
140
160
L
ch
= 7 nm
10 nm
20 nm
30 nm
(b)
(a)
0 mV/V
SS [m V/ dec ]
DIB L [mV /V ]
T
FE
[nm]
60 mV/dec
Fig. 4. (a) DIBL and (b) SS as a function of T
F E
for L
ch
= 7, 10, 20, and
30 nm.
MOSFETs (1.1 mA/µm and 71.5 mV/dec). However, in the
case of NCFETs with T
F E
= 380 nm, the hysteresis behavior is
observed. Inset of Fig. 3 shows the MOS capacitance (C
MOS
)
and C
F E
as a function of Q
G
for NCFETs with T
F E
=
270 and 380 nm. For T
F E
= 270 nm, C
G
is positive in the
all range of Q
G
, because |C
F E
| is larger than C
MOS
. For
T
F E
= 380 nm, on the other hand, |C
F E
| > C
MOS
in a
certain range of Q
G
and so C
G
becomes negative in the range
only. In this condition, NCFETs become unstable, resulting
in the hysteresis behavior [17]. Such a trade-off between
high performance and hysteresis agrees well with previous
results [12][17]. Since hysteresis behavior is not desirable, we
consider only hysteresis-free NCFETs hereafter.
The dependence of DIBL and SS on T
F E
is shown in Fig.
4. Regardless of the hysteresis behavior, we can extract SS and
DIBL for the forward sweep. SS is defined as the minimum
inverse slope near threshold voltage (V
th
), which is defined
as the gate voltage at which I
D
= 0.1 µA/µm for the forward
sweep. It is interesting to note that in the cases of devices with
L
ch
= 20 and 30 nm, DIBL has a value of 0 mV/V when
-0.6
-0.3
0.0
0.3
-0.6
-0.3
0.0
0.3
5 10 15 20 25 30 35
-0.6
-0.3
0.0
0.3
0.5 V
0.3 V
V
DS
= 0.1 V
0.00 0.25 0.50
0.0
0.4
0.8
1.2
0.1 V
0.3 V
V
GS
= 0.5 V
I
D
[mA/ m]
V
DS
[V]
(a)
T
FE
= 0.0 nm
(b)
T
FE
= 170 nm
0.00 0.25 0.50
0
5
10
15
I
D
[mA/ m]
V
DS
[V]
0.00 0.25 0.50
0
3
6
I
D
[mA/ m]
V
DS
[V]
(c)
X [nm]
Po te n tia l en e rg y [e V ]
T
FE
= 270 nm
Fig. 5. Potential profile at V
GS
= 0.0 V for (a) the conventional MOSFET
and NCFETs with (b) T
F E
= 170 and (c) 270 nm. Insets show the output
characteristics of each device.
SS becomes 60 mV/dec. This behavior can be explained by
the fundamental semiconductor theory as follows. First, SS is
defined as
SS =
dV
GS
dlog
10
I
D
=
dV
GS
dφ
s
dφ
s
dlog
10
I
D
= (1+
C
s
C
G
)×
k
B
T
q
ln10,
(6)
where φ
s
, k
B
, T , and q are the surface potential, Boltzmann
constant, temperature, and electronic charge, respectively. Sec-
ondly, DIBL is expressed as
DIBL =
V
hig h
th
− V
low
th
V
hig h
DS
− V
low
DS
, (7)
where V
low(high)
th
is the threshold voltage at low (high)
V
low(high)
DS
. From the fundamental theory of bulk transistors,
V
th
is written as
V
th
= φ
MS
+ 2φ
bi
+
Q
G
C
G
, (8)
where φ
MS
is the work function difference between the gate
metal and semiconductor and φ
bi
is the built-in potential [29].
Assuming that φ
MS
and φ
bi
are not affected by the ferro-
electric, V
th
only depends on Q
G
/C
G
. That is, if the value
4
Fig. 6. (a) V
int
versus V
DS
for the n-type NCFETs with T
F E
= 270 nm
and (b) Q
G
versus V
GS
. Inset of (b) shows the polarization versus electric
field for SrTiO
3
, where the remanent polarization (P
r
) and coercive electric
field (E
c
) are 5.2 µC/cm
2
and 46.6 kV/cm, respectively.
of C
G
is very large (it can be infinite when C
ox
= −C
F E
for NCFETs), DIBL becomes 0 mV/V. At the same time, the
first term of SS, called the body factor, becomes 1, thus, SS
becomes 60 mV/dec at room temperature.
When L
ch
= 7 and 10 nm, we cannot find the specific
T
F E
to satisfy DIBL = 0 mV/V and SS = 60 mV/dec
simultaneously. This is because, as L
ch
decreases, the direct
source-to-drain tunneling current increases. Thus, SS no longer
can be described by Eq. 6. Therefore, when DIBL = 0 mV/V,
SS 6= 60 mV/dec in short-channel devices.
B. Drain-Induced Barrier Raising (DIBR)
In the previous subsection, we showed that when SS
becomes less than 60mV/dec, DIBL has a negative value.
This behavior is in good agreement with Li’s work [18]. To
investigate it in details, we first compare the potential profile
in the channel region of conventional MOSFETs and NCFETs
with T
F E
= 170 and 270 nm, respectively, as shown in Fig.
5. Here, L
ch
is assumed to be 20 nm for these devices. In
the case of the conventional MOSFET, the potential barrier is
lowered with increasing V
DS
, which indicates a typical DIBL.
However, NCFETs show the opposite trend, which we call
drain-induced barrier rising (DIBR).
0.0
0.1
0.2
0.3
0.4
0.5
0.0 0.1 0.2 0.3 0.4 0.5
0.0
0.1
0.2
0.3
0.4
0.5
0.0 0.1 0.2 0.3 0.4 0.5
0.0
0.2
0.4
0.6
0.8
1.0
V
in
= 0.25 V
I
D
[mA/ m]
V
DS
[V]
n-type
p-type
0.0 0.1 0.2 0.3 0.4 0.5
0
2
4
6
8
10
V
in
= 0.25 V
I
D
[mA/ m]
V
DS
[V]
n-type
p-type
(b)
Conventional inverter
NCFET inverter
V
ou t
[V ]
(a)
V
in
[V]
Fig. 7. Voltage transfer characteristics of the NCFET inverters with (a) T
F E
= 170 (n-type) and 140 (p-type) nm and (b) T
F E
= 270 (n-type) and 280
(p-type) nm. Dashed lines represent the voltage transfer characteristics of the
conventional MOSFET. Insets show the road line of the n-type and p-type
NCFETs at V
in
= 0.25 V.
The V
int
values of NCFETs are plotted as a function of
V
DS
with various V
GS
values in Fig. 6(a). To exhibit DIBR
clearly, T
F E
and L
ch
of NCFETs are assumed to be 270
and 20 nm, respectively. From Fig. 6(a), we can see that,
as V
DS
increases, V
int
decreases. In particular, when V
GS
=
0.2 V, V
int
undergoes a steep variation. This behavior can
be elucidated by Fig. 6(b) and Eq. (6). In this case, the
NCFET is operated in the NC region because Q
G
is less than
remanent polarization (P
r
) of 5.2 µC/cm
2
, as seen in Fig.
6(b) and its inset. Due to the small Q
G
in the NC region, the
second term in Eq. (5) is more dominant than the third term.
Moreover, Fig. 6(b) shows that Q
G
for V
DS
= 0.05 V is higher
than that for V
DS
= 0.5 V. As a consequence, Q
G
reduction
with increasing V
DS
leads to a decrease in V
int
, resulting in
DIBR as seen in Fig. 5(b). In addition, variation in V
int
with
respect to V
DS
is well in accordance with the change in Q
G
,
4Q
G
(Q
G
(V
DS
= 0.05 V) − Q
G
(V
DS
= 0.5 V).
As seen in the insets of Fig. 5(b) and (c), NCFETs show
negative differential resistance (NDR) [16][30], which is a dis-
tinctive feature that is not seen in the conventional MOSFET.
In a Gunn diode, known as a transferred-electron device, NDR
is induced by the transition of electrons from a high-mobility
valley to a low-mobility valley [31]. In the case of NCFETs,
however, it occurs due to the reduction of current caused by
DIBR. For instance, when T
F E
= 270 nm, V
int
is reduced from
1.45 to 0.5 V with increasing V
DS
from 0.05 to 0.5 V as shown
in Fig. 6(a), and NDR is induced as a consequence. Moreover,
since DIBR is associated with C
F E
, NDR can be controlled
