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Journal ArticleDOI

RF Extraction of Self-Heating Effects in FinFETs

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TLDR
In this paper, the authors characterized the dynamic self-heating effect in n-channel SOI FinFETs, and the dependence of thermal resistance on finFET geometry is discussed.
Abstract
Multigate semiconductor devices are celebrated for improved electrostatic control and reduced short-channel effects. However, nonplanar architectures suffer from increases of access resistances and capacitances, as well as self-heating effects due to confinement and increased phonon boundary scattering. In silicon-on-insulator (SOI) technology, the self-heating effects are aggravated by the presence of a thick buried oxide with low thermal conductivity, which prevents effective heat removal from the device active region to the Si substrate. Due to the shrinking of device dimensions in the nanometer scale, the thermal time constant that characterizes the dynamic self-heating is significantly reduced, and radio frequency extraction techniques are needed. The dynamic self-heating effect is characterized in n-channel SOI FinFETs, and the dependence of thermal resistance on FinFET geometry is discussed. It is experimentally confirmed that the fin width and the number of parallel fins are the most important parameters for thermal management in FinFETs, whereas fin spacing plays a less significant role.

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Citations
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Journal ArticleDOI

A comprehensive review on microwave FinFET modeling for progressing beyond the state of art

TL;DR: In this paper, the authors provide a clear and exhaustive understanding of the state of art, challenges, and future trends of the FinFET technology from a microwave modeling perspective, and a comparative study of the achieved results is carried out to gain both a useful feedback to investigate the microwave Fin-FET performance as well as a valuable modeling know-how.
Proceedings ArticleDOI

Self-heating on bulk FinFET from 14nm down to 7nm node

TL;DR: In this article, the authors discuss self-heating effects in scaled bulk FinFETs from 14nm to 7nm node based on 3D FEM simulations and experimental measurements.
Journal ArticleDOI

Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability

TL;DR: A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions, which is critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability.
Journal ArticleDOI

A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs

TL;DR: In this article, the thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed for sub-22-nm technologies using the well-calibrated TCAD simulations.
Journal ArticleDOI

Evaluation of 10-nm Bulk FinFET RF Performance—Conventional Versus NC-FinFET

TL;DR: This letter investigates the RF performance of a negative capacitance FinFET using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices, and finds that NC-FinFET’s cut-off frequency is a function of LaTeX, and observes that the self-heating effect in NC-finFET increases with increase ininline-formula.
References
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Journal ArticleDOI

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI

Heat Generation and Transport in Nanometer-Scale Transistors

TL;DR: Trends in transistor geometries and materials, from bulk silicon to carbon nanotubes, along with their implications for the thermal design of electronic systems are surveyed.
Journal ArticleDOI

Self-heating effects in SOI MOSFETs and their measurement by small signal conductance techniques

TL;DR: In this article, a new thermal extraction technique based on an analytically derived expression for the electro-thermal drain conductance in saturation is presented, which can be used confidently over a wide range of bias conditions, with both fully and partially depleted devices.
Journal ArticleDOI

Sub-60-nm quasi-planar FinFETs fabricated using a simplified process

TL;DR: In this article, double-gate MOSFETs with gate and fin dimensions as small as 30 nm have been fabricated using a new, simplified process, and the electrical gate oxide thickness in these devices is determined from the first FinFET capacitance-versus-voltage characteristics obtained to date.
Journal ArticleDOI

SOI thermal impedance extraction methodology and its significance for circuit simulation

TL;DR: In this paper, the authors reported a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs, where the AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance and thermal capacitance associated with the SOI device.
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