Journal ArticleDOI
Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning
Paul Kirsch,P. Sivasubramani,Jiacheng Huang,Chadwin D. Young,Manuel Quevedo-Lopez,Huang-Chun Wen,Huang-Chun Wen,Husam N. Alshareef,K.J. Choi,K.J. Choi,Chanro Park,K. Freeman,Muhammad Mustafa Hussain,Gennadi Bersuker,H.R. Harris,Prashant Majhi,Prashant Majhi,Rino Choi,P. Lysaght,B. H. Lee,H.-H. Tseng,Rajarao Jammy,Rajarao Jammy,T. S. Böscke,Daniel J. Lichtenwalner,Jesse S. Jur,Angus I. Kingon +26 more
TLDR
In this paper, an interface dipole model explaining threshold voltage tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed, which is very similar to the trends in dopant electronegativity (EN) and ionic radius (r) expected for a interfacial dipole mechanism.Abstract:
An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).read more
Citations
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Journal ArticleDOI
High-K materials and metal gates for CMOS applications
John Robertson,Robert M. Wallace +1 more
TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Journal ArticleDOI
Origin of electric dipoles formed at high-k/SiO2 interface
Koji Kita,Akira Toriumi +1 more
TL;DR: In this paper, the authors proposed a model for the physical origin of the dipole formed at high-k/SiO2 interface, where the bonding energy relaxation at the interface explains why the oxygen density difference is the driving force of the oxygen movement.
Journal ArticleDOI
Band offsets, Schottky barrier heights, and their effects on electronic devices
TL;DR: In this paper, the authors review the band line-ups and band offsets between semiconductors, dielectrics, and metals, including the theory, experimental data, and the chemical trends.
Journal ArticleDOI
Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?
TL;DR: High precise IL thickness control in an ultra-thin IL regime (<0.5 nm) will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.
Journal ArticleDOI
integrations and challenges of novel high-k gate stacks in advanced cmos technology
TL;DR: In this article, the authors review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research.
References
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Journal ArticleDOI
Theory of semiconductor heterojunctions: The role of quantum dipoles
TL;DR: In this paper, a simple criterion for zero-dipole band lineups is proposed, which gives excellent agreement with experimental band lineup, and the close connection between heterojunction band line up and Schottky barrier formation is emphasized.
Proceedings ArticleDOI
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
P. Bai,C. Auth,Sridhar Balakrishnan,M. Bost,Ruth A. Brain,V. Chikarmane,R. Heussner,Makarem A. Hussein,Jack Hwang,D. Ingerly,R. James,J. Jeong,C. Kenyon,E. Lee,Seung Hwan Lee,Nick Lindert,Mark Y. Liu,Z. Ma,T. Marieb,Anand Portland Murthy,Ramune Nagisetty,Sanjay Natarajan,J. Neirynck,Andrew Ott,C. Parker,J. Sebastian,R. Shaheed,Swaminathan Sivakumar,Joseph M. Steigerwald,S. Tyagi,Cory E. Weber,Bruce Woolery,Yeoh Andrew W,Kevin Zhang,M. Bohr +34 more
TL;DR: A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented in this article.
Journal ArticleDOI
Interfacial reactions between thin rare-earth-metal oxide films and Si substrates
Haruhiko Ono,Tooru Katsumata +1 more
TL;DR: In this paper, the infrared absorption of the Si-O-Ln bonds increased as the postannealing temperature rose, and the increase was independent of the elements and almost the same as the increases for Ta2O5 and ZrO2.
Journal ArticleDOI
Work function engineering using lanthanum oxide interfacial layers
Husam N. Alshareef,Manuel Quevedo-Lopez,Huang-Chun Wen,R. Harris,Paul Kirsch,Prashant Majhi,Byoung Hun Lee,Raj Jammy,Daniel J. Lichtenwalner,Jesse S. Jur,Angus I. Kingon +10 more
TL;DR: In this paper, a La2O3 capping scheme was developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics, and the viability of the technique was demonstrated using multiple metal gates that normally show mid-gap work function when deposited directly on SiO.
Journal ArticleDOI
Nucleation and growth study of atomic layer deposited HfO 2 gate dielectrics resulting in improved scaling and electron mobility
Paul Kirsch,Manuel Quevedo-Lopez,H.-J. Li,Y. Senzaki,Jeff J. Peterson,Seung-Chul Song,Siddarth A. Krishnan,Naim Moumen,Joel Barnett,Gennadi Bersuker,P. Y. Hung,Byoung Hun Lee,T. Lafford,Qu-Quan Wang,John G. Ekerdt +14 more
TL;DR: In this article, two atomic layer deposition (ALD) chemistries: tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and HfCl4+H2O+O3 were studied as a function of ALD cycle number on Si(100) surfaces.