Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
Study of IC aging on ring oscillator physical unclonable functions
Dinesh Ganta,Leyla Nazhandali +1 more
TL;DR: This work study the effect of device aging on the stability of Ring Oscillator PUFs for different PUF circuit-level choices and operating conditions, and observes that around 4% of the PUF bits are prone to instability due to aging.
Journal ArticleDOI
A lightweight authentication scheme for telecare medical information system
TL;DR: The rapid development of information technology promotes the development and application of Telecare Information System (TMIS), however, TMIS also has security problems such as information leakage as discussed by the authors, which is a serious problem.
Journal ArticleDOI
A Flexible Design Flow for Software IP Binding in FPGA
TL;DR: This work proposes a novel design flow for SWIP binding on a commodity FPGA platform lacking specialized hardcore security facilities and achieves this by leveraging the qualities of a Physical Unclonable Function (PUF) and a tight integration of hardware and software security features.
Journal ArticleDOI
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications
TL;DR: Results show that the proposed chaos-based PUF is robust against modeling attacks and has significantly less overhead compared to traditional systems containing both logic locking and PUF circuitry.
Proceedings ArticleDOI
Location-Aware Authentication and Access Control Concepts and Issues
TL;DR: Current approaches to location-aware authentication, including the notion of context-based flexible authentication policies, and to where-aware access control, are surveyed, with focus on the GEO-RBAC model.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.