Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
20 Years of research on intellectual property protection
TL;DR: The efforts from industry, government, and academia on securing the design IPs in the past 20 years are surveyed with focus on development from academia side.
Proceedings ArticleDOI
A FPGA-based RO PUF with LUT-Based Self-Compare Structure and Adaptive Counter Time Period Tuning
Jiayan Gan,Jun Zhou,Ning Wang +2 more
TL;DR: The proposed PUF improves the uniqueness by LUT-based self-compare structure, which reduces the delay bias from systematic variations without special constraint on place & route and selection of challenge response pairs and improves the reliability by adaptive counter time period tuning based on real-time measured response stability.
Journal ArticleDOI
M-RO PUF: A portable pure digital RO PUF based on Mux unit
Liang Yao,Lu Yingchun,Huaguo Liang,Qian Han,Hong Zhang,Zhengfeng Huang,Cuiyun Jiang,Maoxiang Yi,Lu Yingchun +8 more
TL;DR: In this article, a novel physical unclonable function (PUF) based on the RO ring constructed by the multiplexer is proposed, which can be used as a new strategy for chip identification.
Journal ArticleDOI
Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65nm CMOS
TL;DR: Test results show that the RM-PUFs generate four reconfigurable 128-bit secret keys, and the keys are secure and reliable over a range of ports.
Patent
Identification information generation device and identification information generation method
TL;DR: In this paper, the identification information generation device comprises an information separation means for separating a cryptographic key of k bits and second identification information of (r−m) bits (m is an integer equal to or larger than 1) from first identification information r bits (r is aninteger equal to larger than 2) outputted from an identification information output means which is impossible to physically duplicated and outputs the same response to the same request for response.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.