Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
A PUF based Light Weight Protocol for Secure WiFi Authentication of IoT devices
TL;DR: A PUF based lightweight protocol is proposed which establishes the secure connection utilizing three pairs of challenge-response and generates a random number as a seed key used by the underlying WiFi protocol which proves its effectiveness while incurs less resource and computation overhead.
Proceedings ArticleDOI
DCT based ring oscillator Physical Unclonable Functions
Onur Günlü,Onurcan Iscan +1 more
TL;DR: A new post-processing scheme is proposed for Physical Unclonable Functions (PUFs) based on Ring Oscillators (ROs) that uses the Discrete Cosine Transform (DCT) to decorrelate the RO outputs and improves on existing RO PUFs in terms of uniqueness and the number of extracted bits.
Patent
Tamper-resistant memory integrated circuit and encryption circuit using same
TL;DR: In this paper, the transition probability of a signal line is equalized by input of random-number data supplied from a random number generating circuit using an arbiter circuit, where data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines.
Proceedings ArticleDOI
Robust counterfeit PCB detection exploiting intrinsic trace impedance variations
TL;DR: A novel PCB authentication approach is addressed that creates robust, unique signatures from a PCB based on process-induced variations in its trace impedances that comes at virtually zero design and hardware overhead and can be applied to legacy PCBs.
Journal ArticleDOI
A PUF-based unified identity verification framework for secure IoT hardware via device authentication
Zhao Huang,Quan Wang +1 more
TL;DR: A unified identity verification framework which can provide fine-grained protection for embedded devices against theft attacks from the system level and can uniquely and accurately identify any or all of the thefts to the embedded system hardware at low silicon overhead.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.