Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Posted Content
Physical Security in the Post-quantum Era: A Survey on Side-channel Analysis, Random Number Generators, and Physically Unclonable Functions
TL;DR: The possibility of performing side-channel analysis in the quantum world is discussed and compared to attacks launched in the classic world, and proposals for quantum random number generation and quantum physically unclonable functions are compared to their classic counterparts and further analyzed to give a better understanding of their features, advantages, and shortcomings.
Journal ArticleDOI
PolyPUF: Physically Secure Self-Divergence
TL;DR: The PolyPUF architecture is proposed, a scalable and secure architecture to introduce polymorphic PUF behavior that significantly increases model-building resistivity while maintaining reliability and is the only evaluated approach to withstand highly complex neural network machine-learning attacks.
Proceedings ArticleDOI
PUFSec: Device fingerprint-based security architecture for Internet of Things
TL;DR: This work proposes PUFSec, a new device fingerprint-based security architecture for IoT devices that fundamentally protects attackers from recovering the secret key from public gate delay information and implements its hardware logic in a real-world FPGA board.
Proceedings ArticleDOI
QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function
TL;DR: A novel QUasi-Adiabatic Logic based PUF (QUALPUF) which is designed using energy recovery technique and the proposed design is energy efficient compared to recent designs of hardware PUFs proposed in the literature.
Proceedings ArticleDOI
Design and evaluation of a delay-based FPGA Physically Unclonable Function
Aaron Mills,Sudhanshu Vyas,Michael D. Patterson,Christopher Sabotta,Phillip H. Jones,Joseph Zambreno +5 more
TL;DR: A new Physically Unclonable Function variant was developed on an FPGA, and its quality evaluated, indicating that the design is competitive in terms of repeatability within a given instance, and uniqueness between instances.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.