Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Patent
Integrated circuit tamper detection and response
TL;DR: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits as discussed by the authors, which includes at least one photovoltaic cell coupled with a reactive material.
Proceedings ArticleDOI
Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs
TL;DR: It is shown that the designer of the Ring Oscillator PUFs implemented in FPGAs needs precise control of placement and routing in order to get unique responses and repeatable results for each individual device, especially when the rest of the reconfigurable device should remain up gradable.
Proceedings ArticleDOI
Hardware trust implications of 3-D integration
Ted Huffmire,Timothy E. Levin,Michael Bilzor,Cynthia E. Irvine,Jonathan Valamehr,Mohit Tiwari,Timothy Sherwood,Ryan Kastner +7 more
TL;DR: In this paper, the authors examine the 3D design approach and provide an analysis concluding that the commodity die system need not be independently trustworthy for the system of joined dies to provide certain trustworthy functions.
Proceedings ArticleDOI
Design of low area-overhead ring oscillator PUF with large challenge space
TL;DR: Quality of the proposed scheme has been validated by the design of 60-bit ROPUF on Altera FPGA (Field Programmable Gate Array) that is physically infeasible according to previously proposed direct design principles.
Journal ArticleDOI
MVL‐PUFs: multiple‐valued logic physical unclonable functions
Sha Tao,Elena Dubrova +1 more
TL;DR: It is shown that by extracting device mismatch in either current‐mode or voltage‐mode MVL comparators, the proposed PUF circuits can generate unique and reliable chip identifiers and significantly improve the energy efficiency of the state‐of‐the‐art PUFs.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.