Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
Physically secure mutual authentication for IoT
TL;DR: This work presents mutual authentication protocols for IoT devices that are not only efficient but also secure against physical and cloning attacks, and uses physical unclonable functions (PUFs) to provide security to physically unprotected devices.
Proceedings ArticleDOI
An experimental study of the state-of-the-art PUFs implemented on FPGAs
TL;DR: This paper implements a group of state-of-the-art PUFs on two models of FPGAs and carries out an experimental analysis that evaluates the implemented PUFs, providing useful information for security application developers to devise innovative PUF-utilized security applications as well as PUF design researchers to design PUFs for particular applications.
Proceedings ArticleDOI
Cyber-physical security using system-level PUFs
Omar Al Ibrahim,Suku Nair +1 more
TL;DR: Based on a composition approach, the benefits of combining multiple PUF elements, with some inherently bias factor, into one randomly secure and strong system-level PUF are illustrated.
Journal ArticleDOI
A Method for Detecting Abnormal Program Behavior on Embedded Devices
Xiaojun Zhai,Kofi Appiah,Shoaib Ehsan,Gareth Howells,Huosheng Hu,Dongbing Gu,Klaus D. McDonald-Maier +6 more
TL;DR: A self-organizing map (SOM)-based approach to enhance embedded system security by detecting abnormal program behavior and results show that the proposed method can identify unknown program behaviors not included in the training set with over 98.4% accuracy.
Proceedings ArticleDOI
HSC-IoT: A Hardware and Software Co-Verification Based Authentication Scheme for Internet of Things
TL;DR: HSC-IoT is proposed, a resource-efficient Physical Unclonable Function (PUF)-based security protocol that ensures both software and hardware integrity of IoT devices and provides a lightweight mutual authentication scheme for the resource-limited devices based on Elliptic Curve Cryptography.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.