Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
A highly reliable dual-arbiter PUF for lightweight authentication protocols
TL;DR: A new Dual Arbiter PUF design is introduced that reveals additional information concerning the stability of the outputs, and a novel filtering scheme is employed that discards unreliable outputs with a minimum number of evaluations, greatly reducing the BER of the PUF.
Proceedings ArticleDOI
Reliable and reproducible PUF based cryptographic keys under varying environmental conditions
TL;DR: In this paper, a configurable ring oscillator PUFs (c-ROPUFs) is utilized to improve PUF entropy and reliability and a novel security technique to enhance PUF's reproducibility using a newly defined parameter namely intra-die diverseness is introduced.
Journal ArticleDOI
Practical Experiments to Evaluate Quality Metrics of MRAM-Based Physical Unclonable Functions
Arash Nejat,Frederic Ouattara,Mohammad Mohammadinodoushan,Bertrand Cambou,Ken Mackay,Lionel Torres +5 more
TL;DR: It is demonstrated how voltage values used for writing in the TAS-MRAM cells can make stochastic behaviors required for PUF design, which shows that for key-generation protocols, one of the standard error correction methods should be employed if the proposed PUF is used.
Proceedings ArticleDOI
The Applications of NVM Technology in Hardware Security
TL;DR: This paper summarizes two of the works about using NVM devices to implement these hardware security features and compare them with conventional designs.
Proceedings ArticleDOI
Federated system-to-service authentication and authorization combining PUFs and tokens
TL;DR: This work proposes a new system-to-service authentication and authorization mechanism based on the combination of a Physical Unclonable Function (PUF) and two tokens capable of working over HTTP or COAP relying on federated schemes and adapted to the specific requirements of this kind of environments.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.