Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
Hybrid modeling attacks on current-based PUFs
Raghavan Kumar,Wayne Burleson +1 more
TL;DR: It is demonstrated that the fault-injection attacks when coupled with a machine learning (ML) algorithm can considerably push the limits of prediction accuracies.
Proceedings ArticleDOI
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain
TL;DR: This paper proposes an arbiter based PUF circuit built on current starved inverters, whose drain currents are set by local current mirrors, which amplifies process variations that result in greater uniqueness when compared against a simple inverter chain.
Proceedings ArticleDOI
Hardware authentication leveraging performance limits in detailed simulations and emulations
TL;DR: Each processor design can be authenticated by requiring a checksum incorporating internals of complex microarchitectural mechanisms to be computed within a time limit; this checksum is different for each processor model and only authentic secure hardware can obtain the checksum fast enough.
Proceedings ArticleDOI
Protocol attacks on advanced PUF protocols and countermeasures
Marten van Dijk,Ulrich Rührmair +1 more
TL;DR: The stronger bad PUF model and PUF re-use model are explained, and it is argued why these stronger attack models are realistic, and that existing protocols, if used in practice, will need to face these.
Proceedings ArticleDOI
Novel technique to improve strength of weak arbiter PUF
TL;DR: A unique technique is proposed which takes n × 1 challenge-response pairs from APUF and combines them with ring oscillators implemented on the same FPGA to get n × n CRPs and is claimed to be immune to modeling attacks to a great extent.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.