Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
A pair selection algorithm for robust RO-PUF against environmental variations and aging
TL;DR: This paper proposes a reliable pair selection algorithm (RePa) that can generate reliable keys from an RO-PUF under aging, voltage, and temperature variations, and evaluates it with simulations to show that it achieves significant improvement over the current state of the art in terms of reliability and cost.
Journal ArticleDOI
A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
TL;DR: The experimental results demonstrate that the proposed model accurately estimates the relationship between uniqueness and min-entropy, with both the theoretical analysis and software simulations closely matching the experimental results.
Journal ArticleDOI
A novel memristor based physically unclonable function
TL;DR: A novel hybrid memristor-CMOS XOR/XNOR logic circuit that offers several advantages such as combinational circuit behavior, simpler operation and lower hardware overhead than existing solutions is introduced.
Journal ArticleDOI
Authenticated secret key generation in delay-constrained wireless systems
TL;DR: In this paper, the authors proposed a zero round trip time (0-RTT) resumption authentication protocol combining PUF and SKG processes, and a novel authenticated encryption (AE) using SKG, and pipelining of the AE SKG and the encrypted data transfer in order to reduce latency.
Proceedings ArticleDOI
Secure software update and IP protection for untrusted devices in the Internet of Things via physically unclonable functions
TL;DR: This work proposes a novel protocol by integrating different trust establishing techniques, to allow secure software updates on nodes already infected with malware, which offers stronger IP protection under a more powerful attacker model, while the implementation costs are comparable to those of the existing protocols.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.