Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Journal ArticleDOI
Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs
TL;DR: Two types of on-chip lightweight sensors are proposed to identify recycled ICs by measuring circuit usage time when used in the field, and the analysis of usage time stored in AF-based sensors shows that recycledICs, even used for a very short period, can be accurately identified.
Proceedings ArticleDOI
Low-power sub-threshold design of secure physical unclonable functions
TL;DR: This work optimize the PUF supply voltage for the minimum power-delay product and investigates the trade-offs on PUF uniqueness and reliability and demonstrates that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks.
Patent
Hardware device to physical structure binding and authentication
TL;DR: In this article, a cryptographic fingerprint unit was proposed to authenticate a binding of a hardware device and a physical structure. But the binding logic was coupled with an external PUF value associated with the physical structure, and the binding value represented the binding of the hardware device.
Proceedings ArticleDOI
Performance metrics and empirical results of a PUF cryptographic key generation ASIC
TL;DR: A PUF design with integrated error correction that is robust to various layout implementations and achieves excellent and consistent results in each of the following four areas: Randomness, Uniqueness, Bias and Stability is described.
Book ChapterDOI
MECCA: a robust low-overhead PUF using embedded memory array
TL;DR: A novel memory-cell based PUF is proposed, which performs authentication by exploiting the intrinsic process variations in read/write reliability of cells in static memories, and provides large choice of challenge-response pairs with high uniqueness and excellent reproducibility.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.