Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
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Proceedings ArticleDOI
A noise bifurcation architecture for linear additive physical functions
TL;DR: This work presents the first architecture for linear additive physical functions where the noise seen by the adversary and the noise see by the verifier are bifurcated by using a randomized decimation technique and a novel response recovery method at an authentication verification server.
Proceedings ArticleDOI
Device and technology implications of the Internet of Things
Robert Campbell Aitken,Vikas Chandra,James Edward Myers,Bal S. Sandhu,Lucian Shifren,Greg Yeric +5 more
TL;DR: This talk looks at the trends and discusses some likely paths forward in the Internet of Things, where people interact with the world around them in entirely new ways.
Journal ArticleDOI
CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication
TL;DR: The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures and stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations.
Journal ArticleDOI
A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment
TL;DR: A comprehensive framework has been developed to find an optimum set of detection methods considering test time, test cost, and application risks, and an assessment of all the detection methods based on the newly introduced metrics – counterfeit defect coverage, under- covered defects, and not-covered defects.
Proceedings ArticleDOI
A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs
Xin Xin,Jens-Peter Kaps,Kris Gaj +2 more
TL;DR: Improved Maiti's configurable RO PUFs are analyzed and improvements to generate more output bits are proposed, by utilizing latches as well as the resource mentioned above.
References
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Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.