Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
- pp 9-14
TLDR
This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.Abstract:
Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.read more
Citations
More filters
Proceedings ArticleDOI
Lightweight Mutual Authentication and Ownership Transfer for RFID Systems
TL;DR: This paper proposes a lightweight solution to Mutual Authentication for RFID systems in which only the authenticated readers and tags can successfully communicate with each other and adapts the Mutual Authentication scheme to secure the Ownership Transfer of RFID tags.
Journal ArticleDOI
Physical unclonable functions
TL;DR: The development of physical unclonable functions, which exploit inherent randomness to give a physical entity a unique ‘fingerprint’ or trust anchor, are reviewed, considering the various potential applications of these devices and the security issues that they must confront.
Proceedings ArticleDOI
Silencing Hardware Backdoors
Adam Waksman,Simha Sethumadhavan +1 more
TL;DR: This paper presents the first solution for disabling digital, design-level hardware backdoors by scrambling inputs that are supplied to the hardware units at runtime, making it infeasible for malicious components to acquire the information they need to perform malicious actions.
Proceedings ArticleDOI
Machine learning attacks on 65nm Arbiter PUFs: Accurate modeling poses strict bounds on usability
TL;DR: It is concluded that plain 64-stage Arbiter PUFs are not secure for challenge-response authentication, and the number of extractable secret key bits is limited to at most 600.
Book ChapterDOI
The glitch PUF: a new delay-PUF architecture exploiting glitch shapes
Daisuke Suzuki,Koichi Shimizu +1 more
TL;DR: A new Delay-PUF architecture that is expected to solve the current problem of Delay- PUF that it is easy to predict the relation between delay information and generated information is proposed, and the evaluation results on the randomness and statistical properties are shown.
References
More filters
Journal ArticleDOI
Physical one-way functions
TL;DR: The concept of fabrication complexity is introduced as a way of quantifying the difficulty of materially cloning physical systems with arbitrary internal states as primitives for physical analogs of cryptosystems.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Tamper resistance: a cautionary note
Ross Anderson,Markus G. Kuhn +1 more
TL;DR: It is concluded that trusting tamper resistance is problematic; smartcards are broken routinely, and even a device that was described by a government signals agency as 'the most secure processor generally available' turns out to be vulnerable.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
TL;DR: In this paper, a model describing the maximum clock frequency distribution of a microprocessor is derived and compared with wafer sort data for a recent 0.25-/spl mu/m microprocessor.