This work is operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use, using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator.
Abstract:
Stub Series Terminated Logic (SSTL) is an Input/output standard. It is used to match the impedance of line, port and device of our design under consideration. Therefore, selection of energy efficient SSTL I/O standard among available different class of SSTL logic family in FPGA, plays a vital role to achieve energy efficiency in design under test (DUT). Here, DUT is ROM. ROM is an integral part of processor. Therefore, energy efficient design of RAM is a building block of energy efficient processor. We are using Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator. We are operating ROM with the highest operating frequency of 4th generation i7 processor to test the compatibility of this design with the latest hardware in use. When there is no demand of peak performance, then we can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating our device with 1GHz frequency in place of 4GHz. There is no change in clock power and signal power but SSTL2_H_DCI having 80.24% 83.38% 62.92% and 76.52% and 83.03% more I/O power consumption with respect to SSTL2_I, SST18_I, SSTL2_I_DCI, SSTL2_II, and SSTL15 respectively at 3.3GHz.
TL;DR: A power efficient Floating Point Unit (FPU) as a DPD has been designed in 65nm process technology using Virtex 5 FPGA and its impact on the power consumption of FPU with different IO standards is presented.
TL;DR: This paper analyzes the power of a digital clock with the help of Xilinx ISE V-14.2 and gets a combination of perfect low power consuming IC design and further power utilization using different IO standards at different frequency has been decreased effectively.
TL;DR: This paper designs an efficient memory using LVCMOS and HSTL-I IO Standards on 28 nm (Artix-7) FPGA and finds the most power-efficient circuit when there is 40–60% saving in power dissipation of memory circuits.
TL;DR: A detailed analysis on a low power memory circuit using buffer, extraction and style based RAM design on 28nm Field Programmable Gate Array (FPGA) using Verilog, Xilinx ISE 14.6 simulator with kintex-7 FPGA.
TL;DR: This work is making energy efficient ALU using the most energy efficient LVCMOS IO standard for the highest frequency of i7 processor and making this ALU portable using MOBILE DDR IO standard in place of default LVCmOS33 IO standard which the authors use in traditional ALU.
TL;DR: This paper describes a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads.
TL;DR: This work has used Verilog as HDL and Xilinx ISE 14.6 as simulator to design the voltage based efficient fire sensor and has used four different kinds of Stub Series Terminated Logic (SSTL)IO standards.
TL;DR: To achieve reduction in IOs power, this work is searching the most energy efficient LVCMOS(Low Voltage Complementary Metal Oxide Semiconductor) IO standard, whose power consumption is less in compare to other IO standard.
Q1. What are the contributions mentioned in the paper "Sstl i/o standard based environment friendly energy efficient rom design on fpga" ?
In this paper, the authors used Verilog hardware description language, Virtex-6 FPGA, and Xilinx ISE simulator to test the compatibility of this design with the latest hardware in use.
Q2. What is the conclusion of the research that the authors have studied?
The conclusion of the whole research that the authors have studied is basically, Their ROM is approximately 60% more energy efficient with SSTL18_I IO standard in compare to SSTL2_II_DCI.
Q3. What is the name of the conference?
I. Hatai, I. Chakrabarti, “A high-speed, ROM-less DDFS for software defined radio system”, IEEE International Conference on Communication Control and Computing Technologies (ICCCCT), 2010.
Q4. what is the power dissipation of SSTL18-Ipower?
When there is no demand of peak performance, then the authors can save 74.5% clock power, 75% signal power, and 30.83% I/O power by operating their device with 1GHz frequency in place of 4GHz as shown in Table 2 and Figure 3.Table 3: Power Dissipation with SSTL18-IPower→ Frequency↓Clock Signal IO Total1.0GHz 0.013 0.001 0.413 1.148 2.9GHz 0.037 0.003 0.493 1.257 3.3GHz 0.042 0.004 0.518 1.288 3.6GHz 0.046 0.004 0.539 1.314 3.8GHz 0.048 0.004 0.553 1.331 4.0GHz 0.051 0.004 0.565 1.346