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Showing papers on "Anodic bonding published in 2003"


Journal ArticleDOI
TL;DR: A low energy Ar ion beam of 40-100 eV was used to activate the Cu surface prior to bonding in this paper, which enables successful Cu-Cu direct bonding under an ultrahigh vacuum condition.
Abstract: Thin copper (Cu) films of 80 nm thickness deposited on a diffusion barrier layered 8 in. silicon wafers were directly bonded at room temperature using the surface activated bonding method. A low energy Ar ion beam of 40–100 eV was used to activate the Cu surface prior to bonding. Contacting two surface-activated wafers enables successful Cu–Cu direct bonding. The bonding process was carried out under an ultrahigh vacuum condition. No thermal annealing was required to increase the bonding strength since the bonded interface was strong enough at room temperature. The chemical constitution of the Cu surface was examined by Auger electron spectroscope. It was observed that carbon-based contaminations and native oxides on copper surface were effectively removed by Ar ion beam irradiation for 60 s without any wet cleaning processes. An atomic force microscope study shows that the Ar ion beam process causes no surface roughness degradation. Tensile test results show that high bonding strength equivalent to bulk ...

269 citations


Patent
26 Jun 2003
TL;DR: In this article, the authors propose a method of bonding a wafer to a substrate comprising the steps of: providing a Wafer having a front surface and a back surface, attaching the front surface of the wafer with a support, thinning the wafers back surface; bonding the back surface of Wafers to the substrate using a thin bonding technique; and removing the support from the front surfaces of WAFers.
Abstract: A method of bonding a wafer to a substrate comprising the steps of: providing a wafer having a front surface and a back surface; attaching the front surface of the wafer to a support; thinning the wafer from the back surface; bonding the back surface of the wafer to a substrate using a thin bonding technique; and removing the support from the front surface of the wafer. A circuit comprising: a substrate; and a wafer; wherein the wafer is at most about 50 microns thick; wherein the wafer has a front surface comprising features; and wherein the wafer has a back surface bonded to the substrate using a thin bonding technique.

199 citations


Journal ArticleDOI
Jun Wei, H Xie, M L Nai, C. K. Wong, L C Lee 
TL;DR: In this article, anodic bonding between silicon wafer and glass wafer (Pyrex 7740) has been achieved at low temperature using a tensile testing machine, and the bond strength is measured using the Taguchi method.
Abstract: In this paper, anodic bonding between silicon wafer and glass wafer (Pyrex 7740) has been achieved at low temperature. The bond strength is measured using a tensile testing machine. The interfaces are examined and analyzed by scanning acoustic microscopy (SAM), scanning electron microscopy (SEM) and secondary ion mass spectrometry (SIMS). The effects of the bonding parameters on bond quality are investigated using the Taguchi method. The bonding temperature used ranges from 200 °C to 300 °C. Almost bubble-free interfaces have been obtained. The bonded area increases with increasing bonding temperature. The unbonded area is less than 1.5% within the whole wafer for bonding temperature between 200 °C and 300 °C. The bond strength is higher than 10 MPa and increases with the bonding temperature. Fracture mainly occurs inside the glass wafer other than in the interface when the bonding temperature is higher than 225 °C. Higher bonding temperature results in more oxygen migration to the interface and more Si–O bonds. The bonding mechanisms consist of hydrogen bonding and Si–O chemical reaction.

147 citations


Journal ArticleDOI
TL;DR: In this paper, a preconcentrator-focuser (PCF) was developed to capture and concentrate vapors for subsequent focused thermal desorption and analysis in a micro gas chromatograph.
Abstract: The design, fabrication, and testing of a preconcentrator-focuser (PCF), consisting of a thick micromachined Si heater packed with a small quantity of a granular adsorbent material are described. The PCF is developed to capture and concentrate vapors for subsequent focused thermal desorption and analysis in a micro gas chromatograph. The microheater contains an array of high-aspect-ratio, etched-Si heating elements, 520 /spl mu/m (h)/spl times/50 /spl mu/m (w)/spl times/3000 /spl mu/m (l), bounded by an annulus of Si and thermally isolated from the remaining substrate by an air gap. This structure is sandwiched between Pyrex glass plates with inlet/outlet ports that accept capillary tubes for sample flow and is sealed by anodic bonding (bottom) and rapidly annealed glass/metal/Si solder bonding (top). The large microheater surface area allows for high adsorption capacity and efficient, uniform thermal desorption of vapors captured on the adsorbent within the structure. The adsorbent consists of roughly spherical granules, /spl sim/200 /spl mu/m in diameter, of a high-surface-area, graphitized carbon. Key design considerations, fabrication technologies, and results of performance tests are presented with an emphasis on the thermal desorption characteristics of several representative volatile organic compounds as a function of volumetric flow rates and heating rates. Preconcentration factors as high as 5600 and desorbed peak widths as narrow as 0.8 s are achieved from 0.25-L samples of benzene at modest heating rates. The effects of operating variables on sensitivity, chromatographic resolution, and detection limits are assessed. Testing of this PCF with a micromachined separation column and integrated sensor array is discussed briefly.

147 citations


01 Jul 2003
TL;DR: In this paper, a vacuum packaging process at the wafer level is developed for surface micromachining devices using glass-silicon anodic bonding technology, which is used as a tool for evaluating the vacuum level of the packaging.
Abstract: An ew vacuum packaging process at the wafer level is developed for the surface micromachining devices using glass–silicon anodic bonding technology. The rim for the glass–silicon bonding process which is needed to prevent vacuum leakage is built up simultaneously as the structure is being etched. The mechanical resonator is used as a tool for evaluating the vacuum level of the packaging. The inside pressure of the packaged device wa sm easured indirectly by measuring the quality factor of the mechanical resonator. The measured Q factor was about 5 × 10 4 and the estimated inner pressure was about 1 mTorr. It is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of Ti getter material. The yield of the vacuum packaging process is about 80% and vacuum degradation was not observed after 1000 h had passed. The developed vacuum packaging process is also applied to resonant accelerometers which need a high vacuum environment to implement higher performance. (Some figures in this article are in colour only in the electronic version)

134 citations


Journal ArticleDOI
TL;DR: In this article, a new vacuum packaging process at the wafer level is developed for the surface micromachining devices using glass-silicon anodic bonding technology, which is used as a tool for evaluating the vacuum level of the packaging.
Abstract: A new vacuum packaging process at the wafer level is developed for the surface micromachining devices using glass–silicon anodic bonding technology. The rim for the glass–silicon bonding process which is needed to prevent vacuum leakage is built up simultaneously as the structure is being etched. The mechanical resonator is used as a tool for evaluating the vacuum level of the packaging. The inside pressure of the packaged device was measured indirectly by measuring the quality factor of the mechanical resonator. The measured Q factor was about 5 × 104 and the estimated inner pressure was about 1 mTorr. It is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of Ti getter material. The yield of the vacuum packaging process is about 80% and vacuum degradation was not observed after 1000 h had passed. The developed vacuum packaging process is also applied to resonant accelerometers which need a high vacuum environment to implement higher performance.

126 citations


Journal ArticleDOI
TL;DR: In this paper, an adhesive wafer-level bonding technique is described in which the adhesive material is structured prior to bonding, which can be used to create encapsulated cavities of different heights and sizes for surface micromachined devices directly in the bonding layer.
Abstract: In this work we describe an adhesive wafer-level bonding technique in which the adhesive material is structured prior to bonding. This technique can be used to create encapsulated cavities of different heights and sizes for surface micromachined devices directly in the bonding layer. Benzocyclobutene (BCB) was used as the adhesive bonding material. The structuring of the BCB was done either by dry etching or by using photosensitive BCB. The process parameters needed to achieve a high bond quality while retaining the shapes of the structures in the intermediate bonding layer have been investigated extensively. Both dry-etch and photosensitive BCB were found to be suitable for selective adhesive bonding. The dry-etch BCB must be soft-baked to a polymerisation degree of 50–60% to both withstand the patterning procedure and to be sticky enough for the following bonding. Soft-baking is not necessary for the photosensitive BCB. For both types of BCB, good bond results have been achieved with a bonding pressure of 2–3 bar and full curing of the BCB at 250 °C for 1 h. Furthermore, helium leak tests have been performed to investigate the suitability of selective adhesive bonding for applications with demands on quasi-hermetic seals. Cavities created with this bonding techniques showed a leak rate between 1.4×10−8 and 4.8×10−8 kg m2 s−3 (1.4×10−7 and 4.8×10−7 mbar l s−1), which is 3–10 times higher than the limit of MIL-STD 883E. Therefore, this encapsulation technique does not provide sufficient gas-tightness to fulfill the requirements of hermetic electronic encapsulations.

123 citations


Patent
30 Jun 2003
TL;DR: In this paper, Embodiments of a method of bonding wafers together using a metal interlayer deposited on conductors of each wafer are shown. And a wafer stack is formed according to the method of wafer bonding using an interlayer.
Abstract: Embodiments of a method of bonding wafers together using a metal interlayer deposited on conductors of each wafer. Also disclosed is a wafer stack formed according to the method of wafer bonding using a metal interlayer.

98 citations


Patent
05 Feb 2003
TL;DR: In this paper, a process for bonding oxide-free silicon substrate pairs and other substrates at low temperature is described, which involves modifying the surface of the silicon wafers to create defect regions by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B 2 H 6 plasma.
Abstract: A process for bonding oxide-free silicon substrate pairs and other substrates at low temperature. This process involves modifying the surface of the silicon wafers to create defect regions, for example by plasma-treating the surface to be bonded with a or boron-containing plasmas such as a B 2 H 6 plasma. The surface defect regions may also be created by ion implantation, preferably using boron. The surfaces may also be amorphized. The treated surfaces are placed together, thus forming an attached pair at room temperature in ambient air. The bonding energy reaches approximately 400 mJ/m 2 at room temperature, 900 mJ/m 2 at 150° C., and 1800 mJ/m 2 at 250° C. The bulk silicon fracture energy of 2500 mJ/m 2 was achieved after annealing at 350-400° C. The release of hydrogen from B—H complexes and the subsequent absorption of the hydrogen by the plasma induced modified layers on the bonding surfaces at low temperature is most likely responsible for the enhanced bonding energy.

90 citations


Patent
17 Sep 2003
TL;DR: In this paper, the authors provided a bonding material and a bonding method which enable lead-free bonding that can replace high-temperature soldering, which can be used in a stepwise bonding process containing at least two bonding steps.
Abstract: There is provided a bonding material and a bonding method which enable lead-free bonding that can replace high-temperature soldering. The bonding material of the present invention comprises a dispersion in an organic solvent of composite metallic nano-particles having such a structure that a metal core of a metal particle having an average particle diameter of not more than 100 nm. The bonding material can be advantageously used in a stepwise bonding process containing at least two bonding steps.

90 citations


Journal ArticleDOI
TL;DR: In this article, the authors developed a wafer-scale direct bonding method at room temperature, where four-inch Si wafers are bonded in vacuum after Ar-beam sputter-etching.
Abstract: We have developed a wafer-scale direct bonding method at room temperature. Four-inches Si wafers are bonded in vacuum after Ar-beam sputter-etching. In situ infrared observation indicates that the bonding is achieved spontaneously when two wafers are mated. The specimens bonded at room temperature are so strong that bulk fracture is observed after tensile test. The bonding strength is almost uniform over the 4-in. wafer area. These results demonstrate that neither heat treatment nor applying pressure is required in this bonding method. It is expected that this method provides low-damage assembly and packaging processes suitable for delicate micro-structures.

Journal ArticleDOI
TL;DR: In this paper, the integration of back-side photodiodes with a microfluidic channel network on a single substrate is presented, and the resulting microsystem has all fluidic and electrical connections on one side of the chip.
Abstract: By taking advantage of both the semiconductor properties and the advanced micromachining possibilities of silicon, integration of back-side photodiodes with a microfluidic channel network on a single substrate is accomplished. The resulting microsystem has all fluidic and electrical connections on one side of the chip. Hermetic sealing by anodic bonding is greatly facilitated by the simple topography on the front-side of the chip. To test the chemical functionality and performance of the device a chemiluminescence-based detection scheme is implemented. The introduction and control of the necessary chemical solutions is achieved using a flow injection analysis approach. Hydrogen peroxide is used as a model compound; injected plugs with concentrations in the range of 100 μM to 1 mM are successfully detected.

Journal ArticleDOI
TL;DR: In this paper, the surface roughness was measured by atomic force microscopy and the apparent bonding energy was considered to be proportional to the real area of contact, defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers.
Abstract: Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafer...

Patent
10 Jan 2003
TL;DR: In this paper, a method for producing the LED module, in which metal areas that are suitable as an etching mask improve the impressing of the current required during the anodic bonding, and at the same time, are used as contact areas for contact-connecting the radiation-emitting semiconductor components.
Abstract: An LED module includes a substrate having good thermal conductivity and one or more radiation-emitting semiconductor components that fixed on the top side of the substrate. The underside of the substrate is fixed on a carrier body having a high thermal capacity, in which the component fixing between the semiconductor components and the substrate and the substrate fixing between the substrate and the carrier body are embodied with good thermal conductivity. Furthermore, the invention relates to a method for producing the LED module, in which metal areas that are suitable as an etching mask improve the impressing of the current required during the anodic bonding, and at the same time, are used as contact areas for contact-connecting the radiation-emitting semiconductor components. The LED module has the advantage that the semiconductor components can be subjected to higher energization as a result of the high thermal capacity of the carrier body.

Journal ArticleDOI
TL;DR: In this article, the problems and the solutions presented in this paper are readily applicable to any microelectromechanical system project involving the fabrication of multi-stack structures of two or more wafers containing intricate geometries and large etched areas.
Abstract: Multi-stack wafer bonding is one of the most promising fabrication techniques for creating three-dimensional (3D) microstructures. However, there are several bonding issues that have to be faced and overcome to build multilayered structures successfully. Among these are: (1) chemical residues on surfaces to be bonded originating from the fabrication processes prior to bonding; (2) increased stiffness due to multiple bonded wafers and/or thick wafers; (3) bonding tool effects; (4) defect propagation to other wafer-levels after high-temperature annealing cycles. The problems and the solutions presented here are readily applicable to any microelectromechanical systems project involving the fabrication of multi-stack structures of two or more wafers containing intricate geometries and large etched areas.

Proceedings ArticleDOI
02 Jun 2003
TL;DR: In this paper, the authors evaluated the electrical and mechanical impacts of wafer bonding and thinning processes required for 3D IC fabrication with interconnect structures and showed promising results on wafers with oxide interlevel dielectric (ILD), while some damages observed with the porous low-k ILD.
Abstract: Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.

Journal ArticleDOI
TL;DR: In this article, a low-temperature direct plasma-enhanced chemical vapor deposition (PECVD) oxide to thermal oxide bonding is described, where the PECVD oxide is densified at 350°C and chemical-mechanically polished to obtain reasonably smooth surface for bonding.
Abstract: Low-temperature direct plasma-enhanced chemical vapor deposition (PECVD) oxide to thermal oxide bonding is described. The PECVD oxide is densified at 350 °C and chemical-mechanically polished to obtain reasonably smooth surface for bonding. The PECVD oxide wafer is bonded to the thermal oxide wafer at room temperature after piranha clean that leaves the wafer surfaces hydrophilic. A postbonding anneal at 300 °C completes the bonding. A void-free bonding interface is observed from infrared imaging and the bonding strength is estimated to be 432 mJ/m2. This bonding method can be used in a variety of applications, including three-dimensional integration.

Journal ArticleDOI
TL;DR: In this paper, an atomic-level analysis of the bonding interface on the chip-on-chip (COC) structure utilizing electroplated Au microbumps in 20 µm pitch was performed.
Abstract: Superfine flip-chip bonding technologies in 20 µm pitch microbumps on copper through-hole electrodes are substantial technologies for three-dimensional (3D) chip stacking LSI As the advanced interconnection technology to connect the through-hole electrodes at low temperature and low bonding force, the ultrasonic flip-chip bonding (UFB) was verified by the total evaluation and the atomic-level analysis of the bonding interface on the chip-on-chip (COC) structure utilizing electroplated Au microbumps in 20 µm pitch First, the lower limit bonding conditions were confirmed to be a bonding force of 20 N and an amplitude of 3 µm; the bonding accuracy achieved was within ±2 µm, the electrical interface resistance was stable about 057 Ω, and no damage around the interconnection structure was observed Secondly, the mechanism of solid phase bonding interface formation at the atomic level without solid phase diffusion was confirmed as the Au-Au solid phase UFB bonding mechanism, and the orientation geometry of such bonding was apparently different from that of thermo compression bonding, which showed solid phase diffusion across the boundary The achievement of this research will enable the realization of the 3D chip stacking LSI in the near future, which is characterized by scalabilities and high-performance The subjects are the elucidation of the real oscillation contributes to bonding to optimize the process conditions and the establishment of the micro joint reliabilities utilizing UFB process

Proceedings ArticleDOI
Viorel Dragoi1, Thomas Glinsner1, Gerald Mittendorfer1, Bernhard Wieder1, Paul Lindner1 
TL;DR: In this article, the authors presented results on adhesive bonding using spin-on glass and benzocyclobutene (BCB) from Dow Chemicals. And they illustrated the advantages of using adhesive bonding for MEMS applications by presenting a technology of fabricating GaAs-on-Si substrates.
Abstract: Low temperature wafer bonding is a powerful technique for MEMS/MOEMS devices fabrication and packaging. Among the low temperature processes adhesive bonding focuses a high technological interest. Adhesive wafer bonding is a bonding approach using an intermediate layer for bonding (e.g. glass, polymers, resists, polyimides). The main advantages of this method are: surface planarization, encapsulation of structures on the wafer surface, particle compensation and decrease of annealing temperature after bonding. This paper presents results on adhesive bonding using spin-on glass and Benzocyclobutene (BCB) from Dow Chemicals. The advantages of using adhesive bonding for MEMS applications will be illustrated by presenting a technology of fabricating GaAs-on-Si substrates (up to 150 mm diameter) and results on BCB bonding of Si wafers (200 mm diameter).

Proceedings ArticleDOI
Y. Jin, Z. F. Wang, P.C. Lim, D.Y. Pan, Jun Wei, C.K. Wong 
10 Dec 2003
TL;DR: In this paper, a hermetical sealing technique has been developed, which involves the processes of anodic bonding for silicon and glass wafers with imperfect interface, adhesive bonding, glass frit bonding and silicon-to-gold eutectic bonding.
Abstract: Vacuum packaging is essential for various kinds of microelectromechanical system (MEMS) devices for enhancing the performance and reliability. This paper presents our works on research on vacuum packaging of MEMS devices. A hermetical sealing technique has been developed, which involves the processes of anodic bonding for silicon and glass wafers with imperfect interface, adhesive bonding, glass frit bonding and silicon-to-gold eutectic bonding. Vacuum maintenance has been achieved by applying evaporable and nonevaporable getter films in the packaging process. A specific helium leak detector with bombing system is introduced, which can monitor the deformation of micro diaphragms and conduct leak detection for MEMS structures.

Patent
07 Feb 2003
TL;DR: In this paper, a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pad on the second substrate, and a contact-bonded interface between the first and second set of metamodel interfaces formed by contact bonding of the first nonmetallic regions to the second nonmetal regions.
Abstract: A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

Journal ArticleDOI
TL;DR: In this article, a process for the microfabrication of a wafer-scale palladium-silver alloy membrane (Pd-Ag) is presented, which is suitable for application in hydrogen purification or in dehydrogenation reactors.
Abstract: In this paper, a process for the microfabrication of a wafer-scale palladium-silver alloy membrane (Pd-Ag) is presented Pd-Ag alloy films containing 23 wt% Ag were prepared by co-sputtering from pure Pd and Ag targets The films were deposited on the unetched side of a -oriented silicon wafer in which deep grooves were etched in a concentrated KOH solution, leaving silicon membranes with a thickness of ca 50 /spl mu/m After alloy deposition, the silicon membranes were removed by etching, leaving Pd-Ag membranes Anodic bonding of thick glass plates (containing powder blasted flow channels) to both sides of the silicon substrate was used to package the membranes and create a robust module The hydrogen permeability of the Pd-Ag membranes was determined to be typically 05 mol H/sub 2//m/sup 2//spl middot/s with a minimal selectivity of 550 for H/sub 2/ with respect to He The mechanical strength of the membrane was found to be adequate, pressures of up to 4 bars at room temperature did not break the membrane The results indicate that the membranes are suitable for application in hydrogen purification or in dehydrogenation reactors The presented fabrication method allows the development of a module for industrial applications that consists of a stack of a large number of glass/membrane plates

Journal ArticleDOI
TL;DR: Low-temperature processing is important for bond and exfoliation and materials integration techniques, and bonding in a vacuum or the use of a prebond anneal were able to eliminate interfacial voids up to theAnneal temperature.
Abstract: Low-temperature processing is important for bond and exfoliation and materials integration techniques. Of particular importance for hydrophilic wafer bonding is the reduction and removal of thermally generated voids at the bond interface, i.e., voids not caused by particulates. Possible causes of thermally generated voids are excess water and hydrocarbon contamination, both at the bond interface. Several bonding preparation techniques were explored, and the effects on interfacial void density and bond strength were recorded. After bonding, all wafer pairs were annealed to 250°C. Infrared imaging was used to monitor void formation, and bond strength was measured using the blade insertion method. Microvoids with lateral dimensions greater than 30 μm were imaged using acoustic microscopy. The highest bond strength was 1260 for plasma-cleaned wafers followed closely by 1150 for an HF oxide strip before hydrophilization. In addition to these techniques, bonding in a vacuum or the use of a prebond anneal were able to eliminate interfacial voids up to the anneal temperature. © 2003 The Electrochemical Society. All rights reserved.


Patent
09 Dec 2003
TL;DR: In this article, a plurality of bonding structures and their forming methods for bonding a FPC to a bonding pad, in particular a BPM of a wireless suspension in a head gimbal assembly, using anisotropic conductive adhesive, are presented.
Abstract: A plurality of bonding structures and their forming methods for bonding a FPC to a bonding pad, in particular a bonding pad of a wireless suspension in a head gimbal assembly, using anisotropic conductive adhesive; such structures eliminate the spring-back force in typical anisotropic bonding to ensure durable bonding. At the same time, these structures also allow for reworkability under which the bonded parts can be separated easily.

Patent
Leonard Forbes1
21 May 2003
TL;DR: In this paper, a method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a silicon wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer.
Abstract: A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to the glass substrate. The thin semiconductor layer is formed to a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. An ultra-thin silicon layer bonded to a glass substrate, selected from a group consisting of a fused silica substrate, a fused quartz substrate, and a borosilicate glass substrate, provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Journal ArticleDOI
TL;DR: In this article, a nanometer-scale H trapping defective silicon layer on bonding surfaces was introduced to increase the surface energy of oxide-free, HF dipped, hydrophobic silicon wafers.
Abstract: By introducing a nanometer-scale H trapping defective silicon layer on bonding surfaces, the bonding surface energy of bonded oxide-free, HF dipped, hydrophobic silicon wafers can reach a silicon fracture surface energy of 2500 mJ/m2 at 300 to 400 °C compared with 700 °C conventionally achieved. Adding boron atoms on bonding surfaces can reduce the surface hydrogen release temperature but would not increase the bonding energy unless a defective layer is also formed. This indicates that, in order to achieve high bonding energy, the released hydrogen must be removed from the bonding interface. Many prebonding treatments are available for low-temperature hydrophobic wafer bonding including the formation of an amorphous silicon layer by As+ implantation, by B2H6 or Ar plasma treatment, or by sputter deposition, followed by an HF dip and room temperature bonding in air. The interface amorphous layer may be recrystallized by annealing at elevated temperatures, e.g., at 450 °C for As+-implanted samples.

Journal ArticleDOI
TL;DR: In this article, a plasma polymerized thin films (interlayers) of organosilicon monomers (hexamethyldisiloxane and vinyltriethoxysilane) were deposited in an RF helical coupling plasma system on the glass surface.
Abstract: Unsized glass fibers and planar glass substrates were subjected to low temperature plasma or wet-chemical process to modify the fiber or substrate surface and thus influence the interphase properties of the glass/polyester system. Plasma-polymerized thin films (interlayers) of organosilicon monomers (hexamethyldisiloxane and vinyltriethoxysilane) were deposited in an RF helical coupling plasma system on the glass surface. Commercial silane coupling agent (vinyltriethoxysilane) was coated onto an unmodified glass surface from an aqueous solution. Bonding at the glass/interlayer interface was analyzed by employing a micro-scratch tester together with an optical polarizing microscope for the planar samples. The results revealed that the adhesion bonding could be controlled by plasma process parameters. Scanning electron and atomic force microscopies enabled characterization of the film surface morphology. Chemical composition and chemical structure of prepared interlayers were characterized using X-ray photo...

Proceedings ArticleDOI
04 May 2003
TL;DR: In this article, the authors report on the fabrication of millimeter-sized vapor cells and their performance in atomic clocks based on coherent population trapping (CPT) and discuss two fabrication techniques.
Abstract: We report on the fabrication of millimeter-sized vapor cells and their performance in atomic clocks based on coherent population trapping (CPT). We discuss two fabrication techniques. The first one is based on hollow-core pyrex fibers, fused with a CO/sub 2/ laser or micro-torch, and the second one involves anodic bonding of micro-machined silicon wafers to pyrex. Key aspects of the discussion are the performance of the cell in frequency references, the potential for further miniaturization of the cells and the ability to manufacture them on a large scale with reproducible performance.

Proceedings ArticleDOI
27 May 2003
TL;DR: In this paper, various types of glass substrates have been compared with respect to their suitability as a low-loss substrate in wafer-level chip-scale packaging for RF applications.
Abstract: Various types of glass substrates have been compared with respect to their suitability as a low-loss substrate in waferlevel chipscale packaging for RF applications. Processability has been evaluated by fabrication of shallow and deep recesses using wet etching in HF (iHjP04) solutions. Electrical characteristics (dielectric constant and attenuation) have been extracted from measurements on coplanar wave guides (CPWs) up to 10 GHz. Results show that Coming Pyrex #7740 glass provides optical quality of wet-etched deep recesses, but exhibit about 2 times higher electrical attenuation than Hoya SD-2. Pyrex #7740 and SD-2 are thermally matched to silicon and due to some alkali content, they are suitable for anodic bonding. The relatively high content of A120j (-20%) in SD-2 is favorable for its electrical properties, but makes wet etching of deep recesses more difficult. The non-alkaline AF45, with C'IE almost 2 times of Si (CTEm45=4.5x106 K'), is suitable for adhesive bonding and is difficult to pattern using wet etching. Its electrical attenuation is close to that of SD-2. The measured dielectric constants (at 6 GHz) for SD-2, F'yrex #7740 and AF45 are 4.7,5.9 and 6.1, respectively. Introdnetion