Showing papers on "Channel length modulation published in 2017"

Enhancement-mode Ga2O3 MOSFETs with Si-ion-implanted source and drain

Abstract: Enhancement-mode β-Ga2O3 metal–oxide–semiconductor field-effect transistors with low series resistance were achieved by Si-ion implantation doping of the source/drain contacts and access regions. An unintentionally doped Ga2O3 channel with low background carrier concentration that was fully depleted at a gate bias of 0 V gave rise to a positive threshold voltage without additional constraints on the channel dimensions or device architecture. Transistors with a channel length of 4 µm delivered a maximum drain current density (I DS) of 1.4 mA/mm and an I DS on/off ratio near 106. Nonidealities associated with the Al2O3 gate dielectric as well as their impact on enhancement-mode device performance are discussed.

Printed Organic Inverter Circuits with Ultralow Operating Voltages

Abstract: Low-voltage circuit operation is one of the primary requirements for the practical use of printed electronic devices employing organic thin-film transistors, in particular, the driving of devices with power supplied by energy harvesting using organic solar cells or biofuel cells, which require low-voltage operation, typically below 1 V. This study reports on printed organic inverter circuits that operate at 0.3 V with negligible hysteresis, a gain of greater than 10, and rail-to-rail input and output operation, by utilizing a blend of 2,7-dihexyl-dithieno[2,3-d:2′,3′-d′]benzo[1,2-b:4,5-b′]dithiophene and polystyrene. The ultralow voltage operation of these circuits can be attributed to its finely tunable turn-on voltage, low trap density, ohmic contacts, and minimal channel length modulation coefficients. Moreover, these organic inverter circuit arrays exhibit high uniformity with an average switching voltage of 0.32 ± 0.03 V. As a result, printed organic devices with ultralow operating voltages can be realized with exceptional reproducibility, helping to further the potential of printed electronic applications based on ultralow power organic devices in the future Internet of Things (IoT) ecosystem.

SiC MOSFET design considerations for reliable high voltage operation

Abstract: SiC MOSFETs have demonstrated continued performance improvement and maturation in the areas of Gate oxide stability and reliability over the past years. While necessary, this alone is not sufficient to achieve reliable high voltage operation. In this paper, the design constraints impacting high voltage reliability and their impact on SiC MOSFET performance at useful operating conditions are discussed. Experimental results are demonstrated with industry benchmark, reliable operation of up to T j =200°C with 1.2kV/25mOhm SiC MOSFETs and T j =175°C, 1.7kV/450A all-SiC MOSFET Dual-Switch modules. Avalanche ruggedness of the high-performance devices is also demonstrated with single-pulse energy densities of 9–15J/cm2 recorded with Drain currents as high as ID= 90A for 0.2cm2 die.

3-D analytical modeling of high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual-material bottom gate for suppressing short channel effects

Abstract: This paper presents a detailed study of the response of a new structure namely, high-k gate stack dual-material tri-gate strained silicon-on-nothing MOSFET with dual material bottom gate, towards various short channel effects, namely, drain-induced barrier lowering, threshold voltage roll-off, hot carrier effect and subthreshold swing Based on the 3-D Poisson’s equation, the surface potential of the device is calculated along with its threshold voltage and electric field The impact on the device performance due to the variation of different device parameters is also studied The analytical results are verified using the simulated results obtained from ATLAS, a 3-D device simulator from SILVACO

A comparative study of channel designs for SiC MOSFETs: Accumulation mode channel vs. inversion mode channel

Abstract: This paper provides detailed comparison of electrical characteristics of accumulation mode and inversion mode 1.2 kV SiC MOSFETs, including performance at high temperatures (up to 200 °C). Statistical data measured from over 50 dies on 6-inch SiC wafers was used for this comparison. It is concluded that the accumulation mode SiC MOSFET provides a lower specific on-resistance than the inversion mode MOSFET due to a higher channel mobility (∼ 22 cm2/V·s) while achieving a reasonable threshold voltage (∼ 2.3 V). Based on statistical data analyses, a strong correlation between the threshold voltage and the field effect channel mobility was identified.

Charge based, continuous compact model for the channel current in organic thin-film transistors for all regions of operation

Abstract: In general most modeling approaches for organic field-effect transistors (OFETs) are based on the typical MOSFET equations. The threshold voltage is usually a fitting parameter without relation to physical parameters hence the impact of their variability on the threshold voltage is not clear. The presented modeling approach is charge based with a continuous equation for the channel current in organic field-effect transistors from below to above threshold. The model provides a physics based parameter set related to trap states, and a compatible parameter set from a circuit designer’s perspective. An expression for the threshold voltage is derived depending on the density of trap states. The model considers a power-law mobility model, parasitic contact resistances and channel length modulation effects and is verified with measurements on OFETs fabricated with small molecules.

Negative output differential resistance effect in organic thin film transistors based on pentacene: Characterization and modeling

Abstract: A series of p-channel organic thin film transistors (OTFTs) based on small molecule pentacene semiconductor was fabricated to characterize for developing analytical modeling. In this present work, the effect of channel length variation (2.5–20 μm) on the electrical parameters of the OTFTs was emphasized. As the channel length (L) of the pentacene-TFTs is decreased, some effects such as negative output differential resistance, the threshold voltage shift, an increase in the drain current (transconductance) and an improvement in other parameters may be observed. The highest device performance with the mobility value of 8 × 10−3 cm2 V−1 s−1 was obtained from a short channel device (L = 2.5 μm). Total resistances including contact and channel resistances were extracted and discussed in detail. The results showed that the contact resistance significantly affected the performance of the OTFTs with channel lengths of 2.5 μm and 5 μm. A negative differential resistance (NDR) behavior was obtained from the saturation region of the output characteristics for each device in the case while channel length was decreased from 20 μm to 2.5 μm. This NDR effect is attributed to the trapping and de-trapping mechanism of the mobile charges at the pentacene–metal electrode interface. Finally, an analytical compact model of organic thin film transistor was developed including the effect of contact resistance and gate voltage dependent mobility, simultaneously. The proposed model was validated by comparing the results obtained from the model with those measured. The results show that the proposed model is a good agreement with the experimental transfer data for devices with the channel length value of 2.5 μm, 5 μm, 10 μm and 20 μm.

Drain Extended Tunnel FET—A Novel Power Transistor for RF and Switching Applications

Abstract: For the first time, a novel drain-extended tunnel FET (DeTFET) device is disclosed in this paper, while addressing the need for high-voltage/high-power devices for system-on-chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunneling and associated carrier injection. Device’s intrinsic (dc/switching), analog, and RF performance is compared with the state-of-the-art drain-extended nMOS (DeNMOS) device. The proposed device for 11 V breakdown voltage offers $15\times $ better subthreshold slope, $8\times $ lower off-state leakage, $2\times $ higher ON current, and absence of channel length modulation and drain induced barrier lowering, while keeping $2.5\times $ lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain, and better RF characteristics, when compared with the DeNMOS device. Finally, device design guidelines are presented and scalability, without affecting breakdown voltage, of the proposed device is compared with the DeNMOS device.

Modeling and simulation of enhancement mode p-GaN Gate AlGaN/GaN HEMT for RF circuit switch applications

Abstract: An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d - V ds , I d - V gs , and C - V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.

Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect

Abstract: In this paper, we present an analytical charge-based model for thermal noise power spectral density in fully depleted silicon on insulator (FDSOI) MOSFETs. Two important aspects particular to FDSOI technology, namely, different inversion charges and different effective mobilities at front and back interfaces, are considered in the model. Proposed model is valid from weak to strong inversion regions of operation. Velocity saturation and channel length modulation are also incorporated to properly capture the excess noise in deep submicrometer MOSFETs. To test the quality of the model, standard benchmark tests are performed and asymptotic behavior of the model is validated in all regions of operation. The model is implemented in SPICE and validated with calibrated TCAD simulations as well as with experimental data of high frequency noise for wide range of back biases.

Back Enhanced (BE) SOI MOSFET under non-conventional bias conditions

Abstract: The aim of this work is to investigate the working principle of the new Back Enhanced (BE) SOI MOSFET, under non-conventional bias conditions. This planar BE SOI device with undoped source/drain/channel structure presents the advantage to have very simple fabrication process (without any implantation and electron beam lithography) and can act like a p- or n-type MOS, depending on the back-gate bias condition. Under non-conventional bias condition, many electrical parameters present different behavior. The threshold voltage increases linearly with the drain to source voltage (V DS ) if V DS > 0 and it is constant if V DS DS if it is negative and it is constant if V DS >0 in case of a n-type BE SOI MOSFET. This fact is explained through experimental and simulated data.

Drain current local variability from linear to saturation region in 28 nm bulk NMOSFETs

Abstract: In this work, we investigate the impact of the source - drain series resistance mismatch on the drain current variability in 28 nm bulk MOSFETs. For the first time, a mismatch model including the local fluctuations of the threshold voltage (Vt), the drain current gain factor (β) and the source – drain series resistance (RSD) in both linear and saturation regions is presented. Furthermore, it is demonstrated that the influence of the source – drain series resistance mismatch is attenuated in the saturation region, due to the weaker sensitivity of the drain current variability on the series resistance variation. The experimental results were further verified by numerical simulations of the drain current characteristics with sensitivity analysis of the MOSFET parameters Vt, β and RSD.

Analysis and modeling of zero-threshold voltage native devices with industry standard BSIM6 model

Abstract: In this paper, we present the modeling of zero-threshold voltage (V TH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-V TH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of V DS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (L eff) and channel doping (N SUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

Analytical model and performance investigation of electric potential for junctionless cylindrical surrounding gate (JLCSG) MOSFET

Abstract: In this paper expression for surface potential of a junction less cylindrical surrounding gate (JLCSG) MOSFET has been derived using 2D Poisson's equation. The proposed JLCSG MOSFET has no source/drain junction as the doping of channel region is the same as that of source/drain region. The analytical results are compared with the numerical solution using 2D device simulator. The result shows the variation of channel potential with the applied gate and drain bias voltage. The electrostatic parameters of JLCSG MOSFET such as subthreshold swing (SS), ION/IOFF ratio, the threshold voltage (V t ) and drain induced barrier lowering (DIBL) are investigated through exhaustive device simulation. Further, in this paper various analog/RF performance parameters have also been investigated. The performance figure of merits (FOMs) shows that the proposed device has bright future in higher speed and low power communication circuit applications.

Design of A Novel Highly EMI-Immune CMOS Miller OpAmp Considering Channel Length Modulation

Abstract: This paper presents a novel CMOS Miller operational amplifier (OpAmp) that has high immunity to electromagnetic interference (EMI). The proposed CMOS Miller OpAmp uses the replica concept with the source-buffered technique in order to achieve high EMI immunity across a wide range of frequencies (10 MHz to 1 GHz). The proposed amplifier is designed using the first-order quadratic mathematical model. The modeling includes the body effect and channel length modulation. The circuit has been fabricated using 0.18 $\mu \text{m}$ mixed-mode CMOS technology. Measurement results illustrate how the proposed Miller OpAmp reduces susceptibility to EMI even in the presence of high-amplitude interferences that are as high as 1 Vpp. Experimental results show that the maximum EMI-induced output offset voltage for the proposed Miller OpAmp is less than 10 mV over a wide range of frequencies (10 MHz to 1 GHz) when a 900 mVpp EMI signal is injected into the noninverting input. In contrast, the classic Miller OpAmp generates a maximum output offset voltage of 215 mV at 1 GHz under the same operating conditions. The measured results of the EMI-induced input offset corroborates the circuit simulations.

Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET

Abstract: Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 10 4 , while our four channels GAA MOSFET showed a value of 10 3 . In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm.

2D-EFET — A novel beyond Boltzmann transistor

Abstract: The unprecedented technological success of the electronics industry over the last five decades have been driven by Silicon (Si) technology at the center of which resides the metal oxide semiconductor field effect transistor (MOSFET). Relentless scaling of MOSFET dimensions ensured faster and cheaper computing since more and more transistor could be packed into the same chip area.1 At the same time scaling of supply voltage (VDD) kept the power density practically constant. This golden era of MOSFET scaling often referred to as the Dennard Scaling era had continued for almost three decades. However, around 2005, the voltage scaling ended owing to the fact that further reduction in supply voltage (VDD) resulted in exponential increase in the OFF state current (IOFF) and hence the static power dissipation of the MOSFET. This was a direct consequence of non-scalability of the subthreshold slope (SS) to below 60mV/decade. Note, subthreshold slope is defined as the amount of gate voltage required to change the source to drain current of a MOSFET by one order of magnitude. The non-scalability of SS is the outcome of Boltzmann statistics, the governing physical principle for top of the barrier devices like MOSFETs. Although voltage scaling stopped, length scaling still continued for another decade albeit with new challenges like increasing power density, short channel effects and increasing parasitic. Unfortunately, even for the most advanced FinFET technology length scaling seems extremely challenging. Therefore, it is imminent that both aspects of MOSFET scaling will end very shortly. In order to sustain the growth of the semiconductor industry, it is necessary that novel low power beyond Boltzmann device concepts based on aggressively scalable materials be conceived immediately.

Overcurrent protection circuit for low dropout linear voltage regulator

Abstract: The invention discloses an overcurrent protection circuit for a low dropout linear voltage regulator. The overcurrent protection circuit for the low dropout linear voltage regulator comprises a current sampling circuit, a current comparison circuit and an upward pull circuit, wherein the current sampling circuit samples gate-drain voltage of a power tube of the low dropout linear voltage regulator, and outputs a sampling current to the current comparison circuit, the current comparison circuit mirrors the sampling current through a current mirror, and then compares the sampling current with a current of a current source, and after output current value of the low dropout linear voltage regulator exceeds current protection threshold value, control voltage output by the current comparison circuit powers on the upward pull circuit, and the upward pull circuit pulls up gate end voltage of the power tube of the low dropout linear voltage regulator, and thereby limits increasing of the output current, and plays a part in overcurrent protection. The overcurrent protection circuit for the low dropout linear voltage regulator can effectively restrain channel length modulation effects of a current sampling tube in the current sampling circuit, decreases occurrence rate of the problem that deviation between value of the current sampled by the current sampling circuit and ideal value is overlarge, improves current sampling accuracy of the overcurrent protection circuit, and obtains accurate starting threshold value of the overcurrent protection circuit.

A high gain, low power two stage OpAmp using self cascoding technique for Low Frequency Application

Abstract: A Low Voltage, Low Power, Low Noise and High Gain Two Stage OpAmp configuration utilizing self-cascoding transistors has been proposed. Self cascoding helps in decrease of Channel Length Modulation Effect and aides in accomplishing high output impedance and output voltage swing, thereby improving the gain. The frequency response of the proposed design makes it conceivable to be utilized as a part of Low Frequency Applications. For enhancing the Phase Margin of the proposed design, a zero nulling active resistor has been implemented utilizing Transmission Gates for improvement in dynamic range. Simulations have been performed in Cadence Virtuoso using SCL 180 nm technology parameters and comparative analysis have been done by simulating similar two stage OpAmp structures in same technology and with same transistor area, which demonstrates the effectiveness of the proposed design.

Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model

Abstract: One major concern of channel engineering in nanotransistors is the coupling of the conduction channel to the source/drain contacts. In a number of previous publications, we have developed a semiempirical quantum model in quantitative agreement with three series of experimental transistors. On the basis of this model, an overlap parameter 0 ≤ C ≤ 1 can be defined as a criterion for the quality of the contact-to-channel coupling: A high level of C means good matching between the wave functions in the source/drain and in the conduction channel associated with a low contact-to-channel reflection. We show that a high level of C leads to a high saturation current in the ON-state and a large slope of the transfer characteristic in the OFF-state. Furthermore, relevant for future device miniaturization, we analyze the contribution of the tunneling current to the total drain current. It is seen for a device with a gate length of 26 nm that for all gate voltages, the share of the tunneling current becomes small for small drain voltages. With increasing drain voltage, the contribution of the tunneling current grows considerably showing Fowler–Nordheim oscillations. In the ON-state, the classically allowed current remains dominant for large drain voltages. In the OFF-state, the tunneling current becomes dominant.

DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions

Abstract: This paper presents a 2-D model for the DC drain current of a tunnelling field-effect transistor (TFET) considering the source and the drain depletion regions. Analytical expressions are derived for the surface potential, electric field and the band to band generation rate. The drain current is obtained by numerically integrating the generation rate across the entire device. The model is able to predict the ambipolar current as well as the effects of drain voltage in the saturation region. The model uses a semi-empirical approach to capture the transition between the linear and the saturation regions, which gives an infinitely differentiable transfer characteristics. This model includes the effects of drain voltage, gate metal work function, oxide thickness, and silicon film thickness. The accuracy of the model is confirmed by a comparison with 2-D numerical simulations. It is also demonstrated that the proposed model is scalable down to a channel length of 20 nm.

Study of the variation of the threshold voltage with the doping concentration and channel length

Abstract: Threshold voltage is an important parameter in case of device modelling. Variation of threshold voltage affects significantly the modelling of a device specially in case of short channel MOSFET. Variation of threshold voltage also affects the analysis of circuits. Threshold voltage depends on different parameters like doping concentration, surface potential, channel length, oxide thickness, temperature etc. Threshold voltage also depends on random dopant fluctuation. In wide planar transistors the threshold voltage is essentially independent of the drain-source voltage and is therefore a well defined characteristic, however it is less clear in modern nanometer-sized MOSFETs due to drain induced barrier lowering. Survey of different literatures on device modelling shows the necessity of the study of the variation of the threshold voltage with the doping concentration, channel length and oxide thickness. Here the variation of the threshold voltage has been studied through empirical formula and graphically.

Short-channel drain current model for asymmetric heavily / lightly doped DG MOSFETs

Abstract: The paper presents a drain current model for double gate metal oxide semiconductor field effect transistors (DG MOSFETs) based on a new velocity saturation model that accounts for short-channel velocity saturation effect independently in the front and the back gate controlled channels under asymmetric front and back gate bias and oxide thickness. To determine the front and the back-channel velocity saturation, drain-induced barrier lowering is evaluated by effective gate voltages at the front and back gates obtained from surface potential at the threshold condition after considering symmetric and asymmetric front and back oxide thickness. The model also incorporates surface roughness scattering and ionized impurity scattering to estimate drain current for heavily / lightly doped channel for short-channel asymmetric DG MOSFET and a good agreement has been achieved with TCAD simulations, with a relative error of around 3–7%.

Elimination of the channel current effect on the characterization of MOSFET threshold voltage using junction capacitance measurements

Abstract: An alternative method for an extraction of the MOSFET threshold voltage has been proposed. It is based on an analysis of the MOSFET source-bulk junction capacitance behavior as a function of the gate-source voltage. The effect of the channel current on the threshold voltage extraction is fully eliminated. For the threshold voltage and junction capacitance model parameters non-iterative methods have been used. The proposed method has been demonstrated using a series of MOS transistors manufactured using a standard CMOS technology.

A novel dual-gate nano-scale InGaAs transistor with modified substrate geometry

Abstract: Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology recently. In this paper, a new nano-scale dual-gate MOSFET using Ino.75 Gao.25As is proposed. Multiple designs were simulated with different doping concentration in the source/drain region and the channel stop region to get an excellent I on /I qff . Since current in Metal-Oxide-Semiconductor (MOS) depends on the doping profile of the channel, a careful re-engineering of the channel would improve the MOSFET characteristics. Channel length, Lg of the proposed device is 20 nm which produces a significant amplification and supports large current due to wide channel interaction. Simulation of Ino.75 Gao.25 As MOSFET with Lg = 20 nm, gate-oxide thickness toxGate1 = toxGate2 = 2nm and a width Z = 1000nm, exhibits transconductance gm_max ≈ 293.626 μS/μm, subthreshold slope SS ≈ 70 mV/decade and drain-induced-barrier-lowering DIBL = 41.66 mV/V.