Showing papers on "Low voltage published in 1996"

Electroporation employing user-configured pulsing scheme

Abstract: An electroporation method and apparatus generating and applying an electric field according to a user-specified pulsing scheme. Advantageously, one such pulse includes a low voltage pulse of a first duration, immediately followed by a high voltage of a second duration, immediately followed by a low voltage of a third duration. The low voltage electroporation field accumulates molecules at the surface of a cell, the appropriately high voltage field creates an opening in the cell, and the final low voltage field moves the molecule into the cell. The molecules may be DNA, portions of DNA, chemical agents, the receiving cells may be eggs, platelets, human cells, red blood cells, mammalian cells, plant protoplasts, plant pollen, liposomes, bacteria, fungi, yeast, sperm, or other suitable cells. The molecules are placed in close proximity to the cells, either in the interstitial space in tissue surrounding the cells or in a fluid medium containing the cells.

Design considerations for low-voltage on-board DC/DC modules for next generations of data processing circuits

Abstract: By reducing the power supply voltage, a higher speed, lower power consumption, and higher integration density of data processing ICs can be achieved. Presently, a variety of ICs operating from 3.3 V are available. Next generations of ICs are expected to work even with lower voltages, i.e., in the 1-3 V range, to further enhance their speed-power performance. At the same time, during transients, these new generations of data ICs will present very dynamic loads with high current slew rates. As a result, they will require point-of-load power supplies in order to minimize the effects of the interconnection parasitics. These onboard power supplies will be derived from the existing voltages available in the system (usually 5 or 12 V), and will be required to have high power densities, high efficiencies, and good transient performance. This paper presents design considerations for these on-board power supplies and discusses their performance limits imposed by various circuit and system parasitics.

Simulation of the gasdynamic and electromagnetic processes in low voltage switching arcs

Abstract: The switching arc in a low voltage circuit breaker is a very complex phenomenon, which is determined by the interaction between heat conduction, gas flow, current flow, and magnetic forces. A realistic simulation of the switching arc must consider all these effects. In this paper, a three-dimensional (3-D) simulation model is described, which is based on the differential equations for the mass, momentum, and heat balance. Furthermore, it contains a potential differential equation for the calculation of the current flow and the resulting magnetic field. This set of equations is solved by the finite volume method. First results are presented, which show the shape of the arc and the gas flow while the arc is moving between rail electrodes in a simple arc chamber.

Power quality measurements performed on a low-voltage grid equipped with two wind turbines

Abstract: The power quality of a low-voltage grid with two wind turbines is investigated. Slow voltage variations as well as transients and harmonics are measured and analysed. Furthermore, the spectrum of the power is determined so that the presence of periodic power components can be investigated. Although periodic power fluctuations reaching 10% of the rated power are registered, voltage variations are lower than the prescribed IEC flicker limit at steady-state operation. As the turbines are put on-line, the voltage level is lowered by 3%, which exceeds the flicker limit. The risk for flicker increases if the X/R ratio of the grid is low and if turbines which have a tendency to produce large periodic power fluctuations are used.

Class DE inverters and rectifiers for DC-DC conversion

Abstract: A new family of Class DE inverters and related rectifiers is presented. Based on the Class D RF inverter, the circuits feature Class E switching transitions (zero voltage, zero dv/dt), giving low switching losses despite device capacitance and stored charge, combined with low voltage stress. Matching between inverter and rectifier is considered, time reversal duality is introduced and a family of inverters and rectifiers is presented. The circuits should find application in megahertz DC-DC converters.

Dual energy power supply

Abstract: The disclosed dual energy baggage scanning assembly includes a CT scanning system, and a conveyor belt for transporting items through the CT scanning system, and an improved power supply for the X-ray source of the CT scanner so that a dual energy beam is provided. The power supply alternately powers the X-ray tube of the scanning system at high and low voltage levels at a predetermined rate and comprises at least one high voltage DC power supply for providing a stable, high DC voltage the X-ray tube; means, including at least one waveform generator, for providing a periodic time varying waveform; and coupling means, including a transformer, for coupling the waveform generator to said DC voltage supply so that the total voltage across the cathode and anode of the tube is periodically changed between the high and low voltage levels at the predetermined rate in response to the periodic time varying waveform provided by the waveform generator.

Switched-capacitor DC/DC converters with resonant gate drive

Abstract: In this paper, we examine how switched-capacitor (SC) converters can be used in low-voltage low-power DC/DC applications with power management. Analysis of losses is presented to facilitate SC converter design and optimization. A resonant gate drive is proposed to reduce switching losses and simplify control of switches in SC converters. A closed-loop controller is designed to enable and disable oscillations of the resonant gate drive so that the output DC voltage is well regulated down to zero load and so that high efficiency is maintained for a very wide range of loads. Results are experimentally verified on two low-power (0.2 and 5 W) five-one step-down converters with regulated 3 Vdc output and efficiency greater than 80% in a 100-1 load range.

SOI: materials to systems

Abstract: The continuing volume growth of portable systems with their increasing demand for better performance and autonomy makes SOI a very attractive approach for large volume IC's production dedicated to low voltage, low power, high speed systems. The capability of SOI circuits to operate at 1 V or below even in the case of DRAM's has been demonstrated as the best compromise between speed and power consumption. SOI is also appropriate for the Gigabit DRAM generation and the "system on chip" approach. These market segments will be the volume drivers for SOI but they are not the only markets for which SOI will be a key technology. Radiation-hard circuits, Smart power, MEMS, Mixed signal, High temperature electronics, and integrated optics all profit from the unique SOI structure. Up to now production volume of SOI circuits has been limited by SOI material availability. A new approach called Smart Cut(R) offers an answer both for the high volume production of SOI wafers and also for quality and cost issues. This approach is based on hydrogen implantation and wafer bonding and allows cutting of thin slices of material at the atomic scale. Trends in the SOI activity from material to systems are discussed.

A low-voltage, low-power CMOS delay element

Abstract: A low-voltage, low-power CMOS delay element is proposed. With a unit CMOS inverter load, a delay from 2.6 ns to 76.3 ms is achieved in 0.8 /spl mu/m CMOS technology. Based on a CMOS thyristor concept, the delay value of the proposed element can be varied over a wide range by a control current. The inherent advantage of a CMOS thyristor in low voltage domains enables this delay element to work down to the supply voltage of 1 V while the threshold voltage of the nMOS and pMOS transistors are 840 mV and -770 mV, respectively. The designed delay value is less sensitive to supply voltage and temperature variation than RC-based or CMOS inverter-based delay elements. Temperature compensation and jitter performance in a noisy environment are also discussed.

Low voltage integrators for high-frequency CMOS filters using current mode techniques

Abstract: Low voltage CMOS fully differential integrators for high frequency continuous-time filters using current-mode techniques are presented. Current mode techniques are employed to avoid the use of the floating differential pair, in order to achieve operation at lower supply voltage levels. These high frequency integrators feature good supply noise rejection and power efficiency. Simulated and experimental results are presented verifying theoretical results. An example 10 MHz, 6 pole filter fabricated in 2 /spl mu/m CMOS consumes only 0.7 mW/pole and requires only a single 3.3 V supply voltage.

Detecting delay flaws by very-low-voltage testing

Abstract: The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage-between 2 and 2.5 times the threshold voltage V/sub t/ of the transistors. A delay flaw is a defect that causes a local timing failure but the failure is not severe enough to cause malfunctioning. Delay flaws caused by degraded signals and gates with lower drive capability than expected are considered. This paper investigates the voltage dependence of the effects of delay flaws and derives the test conditions for them.

A new SOI inverter for low power applications

Abstract: The speed degradation in CMOS circuits with the supply voltage reduction is an important obstacle in the scale down of supply voltage. Thus, many attempts to reduce the gate delay have been tried using the dynamic threshold scheme. However, they have limitations in the operation voltage and large leakage current. We propose a new type of SOI inverter gate which has considerably shortened circuit delay with similar energy consumption in the conventional SOI CMOS circuit at low voltage operation. It uses the positive-body bias effect that enhances drain currents when the body is biased positively. The operation principle of the proposed gate, the optimal circuit and device conditions studied by simulations, and the fabrication and measurement data are reported in this paper.

Radio-frequency accelerating system and ring type accelerator provided with the same

Abstract: In a radio-frequency accelerating system, a loop antenna is coupled with at least one of a plurality of magnetic core groups each including a plurality of magnetic cores or with at least one of the plurality of magnetic cores, and an impedance adjusting means is connected to the loop antenna. A relatively low voltage is applied to the impedance adjusting means. Therefore, the impedance adjusting means may be a circuit element having a low withstand voltage and hence the radio-frequency accelerating system can be formed to have a small construction.

An active line conditioner to balance voltages in a three-phase system

Abstract: In this paper a new configuration for an active line conditioner is proposed to correct dynamically voltage unbalances in a three-phase AC system. In the proposed system it is shown that the injection of a correction voltage V/sub inj/ in one phase is sufficient to nullify the negative sequence voltage component in the incoming three phase supply. The resulting three phase voltages at the load terminals are essentially positive sequence voltages and hence are balanced. It is further shown that the kVA requirement of the proposed active line conditioner is small, typically 3% for a ten percentage unbalance in the input supply. The dynamic cancellation of the negative sequence voltage component by the proposed scheme drastically improves the performance of induction motor loads connected to a weak AC system. A thorough analysis of the scheme along with the suitable design guides are presented. Finally selected experimental results on a laboratory prototype active line conditioner are detailed.

Effective calculation of power system low-voltage solutions

Abstract: This paper develops a method for reliably determining the set of low-voltage solutions which are closest to the operable power flow solution These solutions are often used in conjunction with techniques such as energy methods and the voltage instability proximity index for assessing power system voltage stability This paper presents an algorithm which provides good initial guesses for these solutions The results are demonstrated on a small power system and on larger power systems with up to 2000 buses

Passive shunt harmonic filters for low and medium voltage: a cost comparison study

Abstract: This paper presents the cost of 480 V and 13.8 kV passive shunt harmonic filters tuned at 300, 420, 660 and 780 Hz. The cost is presented in function of the kVA of the load served by the filters, the 60 Hz reactive power produced by the filter end the total non60 Hz apparent power of the load. The main conclusion of this work is that for nonlinear loads in excess of 1 MVA it is more economical to use filter centers connected on the 13.8 kV side.

Will your motor insulation survive a new adjustable frequency drive

Abstract: The latest family of insulated-gate-bipolar-transistor (IGBT)-type adjustable-frequency drives (AFDs) produce voltage wavefronts that are extremely fast as a result of increasing carrier frequency. The frequency may be as high as 20 kHz. Motors which are designed for low-voltage sinusoidal power run more efficiently and quieter under this condition. However, the insulation in small- and medium-size motors may experience undesirable stress, resulting in accelerated aging. This aging usually leads to premature failure of motors, sometimes days or months after startup. Even new motors make this an issue. Harsh environments may also add to the problem. This paper presents a practical approach to the motor insulation concerns of applying AFD power to less than 1000 V three-phase older motors and give specification details on new motors for AFD service.

Low voltage battery pack monitoring circuit with adjustable set points

Abstract: A low voltage battery pack monitoring circuit for a battery powered electronic device is disclosed. The circuit utilizes low battery and power failure set point voltages and first and second comparison circuits to compare voltage across the device battery pack to the set point voltages. If the battery pack output voltage falls below the low battery pack set point voltages, the first comparison circuit sends a signal to a microprocessor causing a low battery indicator light to be actuated. If the battery pack output voltage continues to decrease below the power failure set point voltage, the second comparison circuit includes a comparator which changes output state and turns off selected electronic systems of the device and the device enters a suspend mode. The low battery pack set point voltage value and the power failure set point voltage value are determined using an empirical look up table.

A new 1.2 V BiCMOS log-domain integrator for companding current-mode filters

Abstract: New structures of differential and single-ended log-domain integrators are proposed, which can be used for very low supply voltage continuous-time filters. They offer a tuning range of several decades and operate at minimum supply voltages down to 1 V. The single-ended version allows very simple filter structures, whereas the differential one can be driven by signal currents which are much larger than the bias currents (class AB operation).

Method of fabricating a low voltage zener-triggered SCR for ESD protection in integrated circuits

Abstract: The method in accordance with the present invention is compatible with conventional CMOS fabrication processes to form a zener diode and a lateral silicon controlled rectifier constituting an on-chip ESD protection circuit in a semiconductor substrate. The zener diode is composed of a p-type doped region and an n-type doped region, wherein one of the doped regions, formed by deep diffusing impurities from a doped polysilicon layer, is arranged between two adjacent well regions. During an ESD event, the zener diode incurs breakdown to lower the trigger voltage of the lateral SCR device to within a range of about 5-7 Volts to thereby discharge the ESD current prior to damage of an internal circuit being protected.

Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits

Abstract: Transistor models which reproduce the superior device characteristics of fully depleted silicon-on-insulator (SOI) MOSFETs and which are efficient for the design of analogue CMOS circuits are discussed and validated. These analogue models are then used to investigate the significant performance improvement that several basic analogue cells can achieve when optimized in fully depleted SOI CMOS, rather than in bulk CMOS technology. Experimental verifications support this original demonstration of the great potential of fully depleted SOI CMOS for low voltage, low power analogue applications.

Quantitative analysis of very-low-voltage testing

Abstract: Some weak static CMOS chips can be detected by testing them with a very low supply voltage-between 2 and 2.5 times the threshold voltage V/sub t/ of the transistors. A weak chip is one that contains a flaw-an imperfection that does not interfere with correct operation at rated conditions but which may cause intermittent or early-life failures. This paper considers several types of flaws and derives the test conditions for them. It also proposes two approaches for determining the appropriate test speed for very-low-voltage testing.

Memory modules with voltage regulation and level translation

Abstract: Low voltage DRAMs are used on higher voltage memory modules in a way that requires no modification of the DRAMs. "Bus switch" technology and compact low voltage regulators are used at the module level. The low voltage regulator provides a lowered, regulated voltage to DRAMs. The bus switches are used at the inputs and outputs of the DRAMs and effectively protect the DRAM circuitry from voltage swings that could otherwise be damaging.

A low-voltage, low-power microwave SOI MOSFET

Abstract: Summary form only given. Recently, it has been demonstrated that the use of high-resistivity SOI (SIMOX) substrates (5,000 and 10,000 /spl Omega/.cm) yields MOSFETs which offer interesting microwave performances. Indeed unity-gain frequencies (f/sub T/) of 14 and 23.6 GHz and maximum oscillation frequencies (f/sub max/) of 21 and 32 GHz have been reported for effective gate lengths of 0.36 and 0.25 /spl mu/m, respectively, and using supply voltages ranging from 3 to 5 volts. Such devices can be integrated with planar lines to implement MMIC circuits. These transistors were fabricated using a dedicated MOS process, called MICROX/sup TM/, which uses non-standard CMOS features, such as a metal (gold) gate and air-bridge metallisation. In this work, the high-frequency performances of microwave transistors fabricated using a standard fully-depleted SOI CMOS process are described. These devices are, therefore, compatible with analog and digital circuits fabricated using the same low-cost process.

High resolution electron beam lithography using ZEP-520 and KRS resists at low voltage

Abstract: ZEP‐520 and KRS resist systems have been evaluated as candidates for use in low voltage electron beam lithography. ZEP‐520 is a conventional chain scission resist which has a positive tone for over two orders of magnitude in exposure dose. KRS is a chemically amplified resist which can be easily tone reversed with a sensitivity ∼8 μC/cm2 at 1 keV. Both resist systems are shown to have sensitivities ∼1 μC/cm2 for positive tone area exposures to 1 keV electrons. A decrease in contrast in 50 nm thick resist layers is seen when exposure voltage is lowered from 2 to 1 keV, indicating nonuniform energy deposition over the resist thickness. High resolution single pass lines have been transferred into both Si and SiO2 substrates at both low and high voltages in each resist system without using multilayer resist masks. The ZEP‐520 and KRS resists are shown to have resolutions of 50 and 60 nm, respectively, at 1 kV, within a factor of 2 of their high voltage resolutions under identical development conditions. A cusp shaped etch profile in Si allows high aspect ratio 20 nm wide trenches to be fabricated using these resists on bulk Si. Low voltage exposures have been used to pattern gratings with periods as small as 75 and 100 nm in ZEP‐520 and KRS, respectively. Low voltage exposures on SiO2 show no indications of pattern distortion due to charging or proximity effects.

Analysis of floating-body-induced leakage current in 0.15 /spl mu/m SOI DRAM

Abstract: Summary form only given. Degradation of the dynamic retention time in SOI DRAMs is a critical issue in the application of SOI technology to memory devices. One possible degradation mode related with the floating-body effect occurs in a non-selected memory cell storing "1" due to a transient lowering of the threshold voltage (Vth) of the transistor associated with a voltage drop of a data line from a precharge level to 0 V. It was reported that this dynamism can induce a leakage current as high as several mA at low voltage regions. In this paper, the possibility of this degradation mode in a 0.15 /spl mu/m SOI DRAM cell is analyzed in detail considering various device parameters and the design guideline to avoid the degradation is described.

Low‐voltage electrochromic device for photovoltaic‐powered smart windows

Abstract: We report the properties of an all‐solid‐state electrochromic (EC) device that can be switched over a useful range of optical transmissions with voltages below 1 V. This switching voltage is smaller than required by other solid‐state EC devices reported to date. We attribute the lower‐than‐normal switching voltage to the use of a thermally evaporated MgF2 thin film as the lithium ion conducting layer. Electrochemical impedance spectroscopy studies show that high lithium ion conductivity and low interfacial barriers for lithium exchange with the adjacent electrochromic and ion storage layers make MgF2 a good choice for the ion conductor in EC devices. This reduction in switching voltage is a first step toward powering an EC device by an integrated semitransparent single‐junction photovoltaic (PV) cell. In a side‐by‐side bench test, where the EC device is connected to a semitransparent a‐SiC:H PV cell having on open circuit voltage of 0.87 V, a relative transmission change in the EC device of 40% is achieved in less than 60 s.

Mos termination for low power signaling

Abstract: A low power termination method and apparatus. The termination circuit (250) is typically coupled to a bus (260) through an interface node (150) to receive a rising edge of an input voltage signal. A clamping device (200, 210) is coupled to the interface node (150) and coupled to receive a clamping voltage, the clamping voltage being less than a termination voltage. The termination circuit also includes a bias supply providing a bias supply voltage. A control terminal (205, 215) of the clamping device (200, 210) is coupled to receive the bias voltage and clamps the interface node (150) when the input voltage signal exceeds a termination voltage. A bias excursion of the bias voltage may be provided responsive to the rising edge so that the clamping device clamps the interface node before the input voltage signal exceeds the termination voltage. Similarly, a second clamping device biased by a second bias supply may be used. The second clamping device clamps the interface node after the input voltage signal falls below an excursion responsive to a falling edge of the input voltage signal so that the second clamping device clamps the interface node before the input falls below the expected low voltage.

Design considerations and tools for low-voltage digital system design

Abstract: Aggressive voltage scaling to 1 V and below through technology, circuit, and architecture optimization has been proven to be the key to ultra low-power design. The key technology trends for low-voltage operation are presented including low-threshold devices, multiple-threshold devices, and SOI and bulk-CMOS based variable threshold devices. The requirements on CAD tools that allow designers to choose and optimize various technology, circuit, and system parameters are also discussed.