Showing papers on "Phase noise published in 2005"
TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
Abstract: We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.
695 citations
TL;DR: In this article, a 1.8 GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1 8 GHz carrier while drawing 3.2 mA from a 3.5-V supply.
Abstract: A 1.8-GHz LC VCO designed in a 0.18-/spl mu/m CMOS process achieves a very wide tuning range of 73% and measured phase noise of -123.5 dBc/Hz at a 600-kHz offset from a 1.8-GHz carrier while drawing 3.2 mA from a 1.5-V supply. The impacts of wideband operation on start-up constraints and phase noise are discussed. Tuning range is analyzed in terms of fundamental dimensionless design parameters yielding useful design equations. An amplitude calibration technique is used to stabilize performance across the wide band of operation. This amplitude control scheme not only consumes negligible power and area without degrading the phase noise, but also proves to be instrumental in sustaining the VCO performance in the upper end of the frequency range.
348 citations
TL;DR: In this article, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature colpitt-voltage controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVOC topologies.
Abstract: The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.
315 citations
TL;DR: In this article, a transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage.
Abstract: A transformer-feedback voltage-controlled oscillator (TF-VCO) is proposed to achieve low-phase-noise and low-power designs even at a supply below the threshold voltage. The advantages of the proposed TF-VCO are described together with its detailed analysis and its cyclo-stationary characteristic. Two prototypes using the proposed TF-VCO techniques are demonstrated in a standard 0.18-/spl mu/m CMOS process. The first design using two single-ended transformers is operated at 1.4 GHz at a 0.35-V supply using PMOS transistors whose threshold voltage is around 0.52 V. The power consumption is 1.46 mW while the measured phase noise is -128.6 dBc/Hz at 1-MHz frequency offset. Using an optimum differential transformer to maximize quality factor and to minimize the chip area, the second design is operated at 3.8 GHz at a 0.5-V supply with power consumption of 570 /spl mu/W and a measured phase noise of -119 dBc/Hz at 1-MHz frequency offset. The figures of merits are comparable or better to that of other state-of-the-art VCO designs operating at much higher supply voltage.
309 citations
TL;DR: In this paper, a study of phase noise in CMOS Colpitts and LC-tank oscillators is presented, which shows that the latter is capable of a 2dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted.
Abstract: This paper presents a study of phase noise in CMOS Colpitts and LC-tank oscillators. Closed-form symbolic formulas for the 1/f/sup 2/ phase-noise region are derived for both the Colpitts oscillator (either single-ended or differential) and the LC-tank oscillator, yielding highly accurate results under very general assumptions. A comparison between the differential Colpitts and the LC-tank oscillator is also carried out, which shows that the latter is capable of a 2-dB lower phase-noise figure-of-merit (FoM) when simplified oscillator designs and ideal MOS models are adopted. Several prototypes of both Colpitts and LC-tank oscillators have been implemented in a 0.35-/spl mu/m CMOS process. The best performance of the LC-tank oscillators shows a phase noise of -142dBc/Hz at 3-MHz offset frequency from a 2.9-GHz carrier with a 16-mW power consumption, resulting in an excellent FoM of /spl sim/189 dBc/Hz. For the same oscillation frequency, the FoM displayed by the differential Colpitts oscillators is /spl sim/5 dB lower.
280 citations
TL;DR: The compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise and thus enables low-cost zero-IF receivers.
Abstract: Nowadays, a lot of effort is spent on developing inexpensive orthogonal frequency-division multiplexing (OFDM) receivers. Especially, zero intermediate frequency (zero-IF) receivers are very appealing, because they avoid costly IF filters. However, zero-IF front-ends also introduce significant additional front-end distortion, such as IQ imbalance. Moreover, zero-IF does not solve the phase noise problem. Unfortunately, OFDM is very sensitive to the receiver nonidealities IQ imbalance and phase noise. Therefore, we developed a new estimation/compensation scheme to jointly combat the IQ imbalance and phase noise at baseband. In this letter, we describe the algorithms and present the performance results. Our compensation scheme eliminates the IQ imbalance based on one OFDM symbol and performs well in the presence of phase noise. The compensation scheme has a fast convergence and a small residual degradation: even for large IQ imbalance, the overall system performance for an OFDM-wireless local area network (WLAN) case study is within 0.6 dB of the optimal case. As such, our approach greatly relaxes the mismatch specifications and thus enables low-cost zero-IF receivers.
217 citations
TL;DR: In this paper, phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated, and the degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors.
Abstract: Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.
216 citations
TL;DR: In this article, the phase-domain phase-locked loops (PLLs) are replaced by a time-to-digital converter and a simple digital loop filter, and the measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications.
Abstract: A fully digital frequency synthesizer for RF wireless applications has recently been proposed. At its foundation lies a digitally controlled oscillator that deliberately avoids any analog tuning controls. When implemented in a digital deep-submicrometer CMOS process, the proposed architecture appears more advantageous over conventional charge-pump-based phase-locked loops (PLLs), since it exploits signal processing capabilities of digital circuits and avoids relying on the fine voltage resolution of analog circuits. An actual implementation of an all-digital PLL (ADPLL)-based local oscillator and transmitter used in a commercial 0.13-/spl mu/m CMOS single-chip Bluetooth radio has recently been disclosed. The conventional phase/frequency detector, charge pump and RC loop filter are replaced by a time-to-digital converter and a simple digital loop filter. Due to the lack of the correlational phase detection mechanism, the loop does not contribute to the reference spurs. The measured close-in phase noise of -86 dBc/Hz is adequate even for Global System for Mobile communications (GSM) applications. In this paper, we present the mathematical description and operational details of the phase-domain ADPLL.
215 citations
IBM1
TL;DR: In this paper, a two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer (FFE) in the transmitter and a five-tap decision-feedback equalizer in the receiver has been designed in 0.13-/spl mu/m CMOS.
Abstract: A 4.9-6.4-Gb/s two-level SerDes ASIC I/O core employing a four-tap feed-forward equalizer (FFE) in the transmitter and a five-tap decision-feedback equalizer (DFE) in the receiver has been designed in 0.13-/spl mu/m CMOS. The transmitter features a total jitter (TJ) of 35 ps p-p at 10/sup -12/ bit error rate (BER) and can output up to 1200 mVppd into a 100-/spl Omega/ differential load. Low jitter is achieved through the use of an LC-tank-based VCO/PLL system that achieves a typical random jitter of 0.6 ps over a phase noise integration range from 6 MHz to 3.2 GHz. The receiver features a variable-gain amplifier (VGA) with gain ranging from -6to +10dB in /spl sim/1dB steps, an analog peaking amplifier, and a continuously adapted DFE-based data slicer that uses a hybrid speculative/dynamic feedback architecture optimized for high-speed operation. The receiver system is designed to operate with a signal level ranging from 50 to 1200 mVppd. Error-free operation of the system has been demonstrated on lossy transmission line channels with over 32-dB loss at the Nyquist (1/2 Bd rate) frequency. The Tx/Rx pair with amortized PLL power consumes 290 mW of power from a 1.2-V supply while driving 600 mVppd and uses a die area of 0.79 mm/sup 2/.
208 citations
TL;DR: In this paper, a new injection-locked dual opto-electronic oscillator (OEO) that uses a long optical fiber loop master oscillator to injection lock into a short-loop signal-mode slave oscillator was reported.
Abstract: We report a new injection-locked dual opto-electronic oscillator (OEO) that uses a long optical fiber loop master oscillator to injection lock into a short-loop signal-mode slave oscillator, which showed substantial improvements in reducing the phase noise and spurs compared to current state-of-the-art multiloop OEOs operating at 10 GHz. Preliminary phase-noise measurement indicated approximately 140-dB reduction of the spurious level.
201 citations
TL;DR: In this article, a low voltage multiband allpMOS VCO was fabricated in a 0.18/spl mu/m CMOS process using a combination of inductor and capacitor switching, four band operation was realized using a single VCO.
Abstract: A low voltage multiband all-pMOS VCO was fabricated in a 0.18-/spl mu/m CMOS process. By using a combination of inductor and capacitor switching, four band (2.4, 2.5, 4.7, and 5 GHz) operation was realized using a single VCO. The VCO with an 1-V power supply has phase noises at 1-MHz offset from a 4.7-GHz carrier of -126 dBc/Hz and -134 dBc/Hz from a 2.4-GHz carrier. The VCO consumes 4.6 mW at 2.4 and 2.5 GHz, and 6 mW at 4.7 and 5 GHz, respectively. At 4.7 GHz, the VCO also achieves -80 dBc/Hz phase noise at 10-kHz offset with 2 mW power consumption.
29 Aug 2005
TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.
Abstract: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS. It transmits GMSK with 0.5/spl deg/ rms phase error and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time. A digitally controlled 6dBm class-E PA modulates the amplitude and meets the EDGE spectral mask with 3.5% EVM.
TL;DR: This work proposes and demonstrates the first RF digitally controlled oscillator (DCO) for cellular mobile phones and analyzes the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and shows that it can be made sufficiently small.
Abstract: We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.
TL;DR: Femtosecond laser frequency combs are used to convert optical frequency references to the microwave domain, where the synthesis of 10-GHz signals having a fractional frequency instability of < or =3.3 fs is demonstrated.
Abstract: We use femtosecond laser frequency combs to convert optical frequency references to the microwave domain, where we demonstrate the synthesis of 10-GHz signals having a fractional frequency instability of ??3.5×10?15 at a 1-s averaging time, limited by the optical reference. The residual instability and phase noise of the femtosecond-laser-based frequency synthesizers are 6.5×10?16 at 1s and ?98dBc?Hz at a 1-Hz offset from the 10-GHz carrier, respectively. The timing jitter of the microwave signals is 3.3fs.
05 Dec 2005
TL;DR: A noise cancellation technique to reduce the flicker-noise contribution of the switches in a Gilbert-type mixer is presented and a prototype double-balanced mixer in 0.13 /spl mu/m CMOS is fabricated as a proof of concept.
Abstract: Based on the physical understanding of noise mechanisms in active mixers, a noise cancellation technique to reduce the flicker noise contribution of the switches in a Gilbert-type mixer is presented. For the proof of concept, a prototype double-balanced mixer in 0.13 /spl mu/m CMOS is fabricated. The circuit achieves a flicker noise corner of almost an order of magnitude lower than that of a standard implementation, without any penalty in the linearity, gain, or power consumption.
TL;DR: A new scheme for stabilizing the carrier-envelope (CE) phase of a few-cycle laser pulse train is demonstrated, which obviates the need for splitting off a fraction of the laser output for CE phase control, coupling into microstructured fiber, and separation and recombination of spectral components.
Abstract: A new scheme for stabilizing the carrier-envelope (CE) phase of a few-cycle laser pulse train is demonstrated. Self-phase modulation and difference-frequency generation in a single periodically poled lithium niobate crystal that transmits the main laser beam allows CE phase locking directly in the usable output. The monolithic scheme obviates the need for splitting off a fraction of the laser output for CE phase control, coupling into microstructured fiber, and separation and recombination of spectral components. As a consequence, the output yields 6-fs, 800-nm pulses with an unprecedented degree of short- and long-term reproducibility of the electric field waveform.
Posted Content•
TL;DR: In this paper, the sensitivity of a time-domain atomic interferometer to the phase noise of the lasers used to manipulate the atomic wavepackets was analyzed, and the sensitivity function was calculated in the case of a three-pulse Mach-Zehnder interferer, which is the configuration of the two inertial sensors we are building at BNM-SYRTE.
Abstract: We present here an analysis of the sensitivity of a time-domain atomic interferometer to the phase noise of the lasers used to manipulate the atomic wave-packets. The sensitivity function is calculated in the case of a three pulse Mach-Zehnder interferometer, which is the configuration of the two inertial sensors we are building at BNM-SYRTE. We successfully compare this calculation to experimental measurements. The sensitivity of the interferometer is limited by the phase noise of the lasers, as well as by residual vibrations. We evaluate the performance that could be obtained with state of the art quartz oscillators, as well as the impact of the residual phase noise of the phase-lock loop. Requirements on the level of vibrations is derived from the same formalism.
TL;DR: Large white noise can lead to desynchronization of oscillators, provided they are non-isochronous, and this is demonstrated for the Van der Pol-Duffing system.
Abstract: We consider the effect of external noise on the dynamics of limit cycle oscillators. The Lyapunov exponent becomes negative under influence of small white noise, what means synchronization of two or more identical systems subject to common noise. We analytically study the effect of small nonidentities in the oscillators and in the noise, and derive statistical characteristics of deviations from the perfect synchrony. Large white noise can lead to desynchronization of oscillators, provided they are nonisochronous. This is demonstrated for the Van der Pol--Duffing system.
TL;DR: In this article, the authors present the analytical formulation of this limit for relaxation (including ring) oscillators using a time-domain phase-noise analysis method which is introduced in this paper.
Abstract: To make RC oscillators suitable for RF applications, their typically poor phase-noise characteristics must be improved. We show that, for a given power consumption, this improvement is fundamentally limited by the fluctuation-dissipation theorem of thermodynamics. We also present the analytical formulation of this limit for relaxation (including ring) oscillators using a time-domain phase-noise analysis method which is introduced in this paper. Measurement shows the maximum possible improvement is generally less than 6dB for ring oscillators, while it can be as high as 21dB for other relaxation oscillators. The suboptimal performance of relaxation oscillators is attributed to the continuous current flow in these oscillator topologies. These results provide useful insight for feasibility studies of oscillator design.
Book•
11 Nov 2005
TL;DR: In this paper, the authors propose a deterministic and random Oscillator with additive noise and additive noise, as well as a Nonlinear Oscillators with Additive Noise.
Abstract: * Deterministic and Random Oscillators * White and Colored Noise * Brownian Motion * Overdamped Harmonic Oscillator with Additive Noise * Overdamped Harmonic Oscillator with Multiplicative Noise * Overdamped Single-Well Oscillator * Overdamped Double-Well Oscillator * Harmonic Oscillator with Additive Noise * Nonlinear Oscillator with Additive Noise * Harmonic Oscillator with Random Frequency * Harmonic Oscillator with Random Damping * Nonlinear Oscillator with Multiplicative Noise
TL;DR: A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process, which is a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadratures VCO.
Abstract: A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner and an high I-Q accuracy quadrature VCO. Measured noise figure is 3.5 dB with an 1/f noise corner of 200 kHz, and an IIP3 of -2 dBm. The synthesizer DSB phase noise integrated over a 10 MHz band is less than -36 dBc while its I-Q phase unbalance is below 1 degree.
TL;DR: A 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications that aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation so coupling between voltage-controlled oscillators in adjacent channels can be avoided.
Abstract: This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.
TL;DR: In this paper, a low-noise synthesis of a harmonic comb of microwave frequencies using a 1 GHz femtosecond-laser-based synthesiser that is referenced to a cavity-stabilised laser is demonstrated.
Abstract: The low-noise synthesis of a harmonic comb of microwave frequencies using a 1 GHz femtosecond-laser-based synthesiser that is referenced to a cavity-stabilised laser is demonstrated. The residual phase noise is /spl sim/-110 dBc/Hz at 1 Hz offset from the 10 GHz harmonic. Phase noise is measured with an interferometric measurement system having low sensitivity to AM.
25 Jul 2005
TL;DR: It is shown that the uncompensated phase noise may cause a time-variant shift, spurious sidelobes, and a broadening of the impulse response, as well as a low-frequency phase modulation of the focused SAR signal.
Abstract: This letter addresses the impact of limited oscillator stability in bistatic and multistatic synthetic aperture radars (SARs). Oscillator noise deserves special attention in distributed SAR systems since there is no cancellation of low-frequency phase errors as in a monostatic SAR, where the same oscillator signal is used for modulation and demodulation. It is shown that the uncompensated phase noise may cause a time-variant shift, spurious sidelobes, and a broadening of the impulse response, as well as a low-frequency phase modulation of the focused SAR signal. Quantitative estimates are derived analytically for each of these errors based on a system-theoretic model taking into account the second-order statistics of the oscillator phase noise
TL;DR: A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated and has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.
Abstract: A novel simulation technique that uses an event-driven VHDL simulator to model phase noise behavior of an RF oscillator for wireless applications is proposed and demonstrated. The technique is well suited to investigate complex interactions in large system-on-chip systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristic comprising of flat electronic noise, as well as, upconverted thermal and 1/f noise regions are described using time-domain equations and simulated as either accumulative or nonaccumulative random perturbations of the fundamental oscillator period. The VHDL simulation environment was selected for its high simulation speed, the direct correlation between the simulated and built circuits and its ability to model mixed-signal systems of high complexity. The presented simulation technique has been successfully applied and validated in a Bluetooth transceiver integrated circuit fabricated in a digital 130-nm process.
TL;DR: A novel signal-processing algorithm based on frequency estimation of the spectrogram of single-mode optical fiber Fabry-Perot interferometric sensors under white-light illumination that can be used for a relatively large cavity length without the need for spectrogram normalization to the spectrum of the light source.
Abstract: A novel signal-processing algorithm based on frequency estimation of the spectrogram of single-mode optical fiber Fabry-Perot interferometric sensors under white-light illumination is described. The frequency-estimation approach is based on linear regression of the instantaneous phase of an analytical signal, which can be obtained by preprocessing the original spectrogram with a bandpass filter. This method can be used for a relatively large cavity length without the need for spectrogram normalization to the spectrum of the light source and can be extended directly to a multiplexed sensor system. Experimental results show that the method can yield both absolute measurement with high resolution and a large dynamic range. Performance analysis shows that the method is tolerant of background noise and variations of the source spectrum.
29 Aug 2005
TL;DR: The proposed LC-VCO is implemented in a 0.18 /spl mu/m CMOS technology for 2GHz applications and measurements show phase noise is -103dBc/Hz at 100kHz offset while dissipating 1mW from a 1.25V supply.
Abstract: An LC-VCO with halt of the power dissipation of a that of the conventional topology is presented. The LC-VCO replaces one of the NMOSFET of the conventional differential LC-VCO with a PMOSFET. The operational principles and design guidelines of the proposed topology are reported. The proposed LC-VCO is implemented in a 0.18 /spl mu/m CMOS technology for 2GHz applications and measurements show phase noise is -103dBc/Hz at 100kHz offset while dissipating 1mW from a 1.25V supply.
TL;DR: In this article, a dual-band transceiver for 2.4-and 5.2-GHz multistandard wireless local area networks is proposed, which integrates a concurrent dualband front-end, a triple-band frequency synthesizer, and a band-sharing in-phase/quadrature modulator/demodulator to maximize component and power reuse.
Abstract: A new dual-band RF transceiver is presented for 2.4- and 5.2-GHz multistandard wireless local area networks. The proposed dual-band RF transceiver integrates a concurrent dual-band front-end, a triple-band frequency synthesizer, and a band-sharing in-phase/quadrature modulator/demodulator to maximize component and power reuse. The design is started with the examination of an enhanced dual-band heterodyne architecture and then the optimal circuit partition to satisfy the multistandard requirements. Key dual-band circuits are designed and integrated with other building blocks for experimental demonstration. The measurement shows that eight 5-GHz channels and 13 2.4-GHz channels can be synthesized within 130 /spl mu/s with phase noise less than -98 dBc/Hz at 100-kHz off carrier and spur suppression greater than -65 dBc. The transmitted P/sub 1 dB/ power is 25/20 dBm at 2.4/5.2 GHz, respectively, with the modulation accuracy error-vector magnitude (EVM) values varying from 3.57% to 7.19%. The receiver gain is 20/31 dB at 2.4/5.2 GHz front-end and 70 dB at IF back-end with EVM within 2.32% to 10% from -70- to -17-dBm received power range.
14 Feb 2005
TL;DR: In this article, the authors developed a 27 and 40 GHz tuned amplifier and a 52.5 GHz voltage-controlled oscillator using 0.18mum CMOS for millimeter-wave design.
Abstract: We have developed a 27- and 40-GHz tuned amplifier and a 52.5-GHz voltage-controlled oscillator using 0.18-mum CMOS. The line-reflect-line calibrations with a microstrip-line structure, consisting of metal1 and metal6, was quite effective to extract the accurate S-parameters for the intrinsic transistor on an Si substrate and realized the precise design. Using this technique, we obtained a 17-dB gain and 14-dBm output power at 27 GHz for the tuned amplifier. We also obtained a 7-dB gain and a 10.4-dBm output power with a good input and output return loss at 40 GHz. Additionally, we obtained an oscillation frequency of 52.5 GHz with phase noise of -86 dBc/Hz at a 1-MHz offset. These results indicate that our proposed technique is suitable for CMOS millimeter-wave design
TL;DR: In this article, the effects of laser phase noise and additive white Gaussian noise (AWGN), which can arise from local oscillator (LO) shot noise or LO-spontaneous beat noise, were considered.
Abstract: We investigate carrier synchronization for coherent detection of optical signals encoding 3 and 4 bits/symbol. We consider the effects of laser phase noise and of additive white Gaussian noise (AWGN), which can arise from local oscillator (LO) shot noise or LO-spontaneous beat noise. We identify 8- and 16-ary quadrature amplitude modulation (QAM) schemes that perform well when the receiver phase-locked loop (PLL) tracks the instantaneous signal phase with moderate phase error. We propose implementations of 8- and 16-QAM transmitters using Mach-Zehnder (MZ) modulators. We outline a numerical method for computing the bit error rate (BER) of 8- and 16-QAM in the presence of AWGN and phase error. It is found that these schemes can tolerate phase-error standard deviations of 2.48/spl deg/ and 1.24/spl deg/, respectively, for a power penalty of 0.5 dB at a BER of 10/sup -9/. We propose a suitable PLL design and analyze its performance, taking account of laser phase noise, AWGN, and propagation delay within the PLL. Our analysis shows that the phase error depends on the constellation penalty, which is the mean power of constellation symbols times the mean inverse power. We establish a procedure for finding the optimal PLL natural frequency, and determine tolerable laser linewidths and PLL propagation delays. For zero propagation delay, 8- and 16-QAM can tolerate linewidth-to-bit-rate ratios of 1.8/spl times/10/sup -5/ and 1.4/spl times/10/sup -6/, respectively, assuming a total penalty of 1.0 dB.