Showing papers on "Polycrystalline silicon published in 1996"

Formation and stability of silicides on polycrystalline silicon

Abstract: Silicides are widely used in silicon integrated circuits as contacts and interconnections. In many applications silicides are used on polycrystalline silicon (polysilicon) such as the gates of FETs and the emitter of bipolar transistors. The use of silicide on polysilicon structures presents a number of unique challenges both in formation of the silicide and in morphological stability during high temperature processing. The purpose of this paper is to review the formation, morphology, and thermal stability of silicides on polysilicon. Mechanisms for silicide roughening on polysilicon are discussed including non-uniform initial reactions, agglomeration, and silicide enhanced grain growth. Results for silicides on polysilicon are compared with those on single crystal Si where relevant, A detailed description of silicide instability and device degradation is presented for a number of silicides, emphasizing TiSi 2 , CoSi 2 , and WSi 2 . Finally, methods for improving the stability of silicides on polysilicon are discussed.

High-quality polycrystalline silicon thin film prepared by a solid phase crystallization method

Abstract: We succeeded in fabricating high-quality polycrystalline silicon (poly-Si) thin films with no boundary from the bottom surface to the top, and achieved an extremely high electron mobility of 808 cm2/V s by a solid phase crystallization (SPC) method. This film was obtained by using a new nucleation layer with 1000 A wide single-crystalline grains embedded in a matrix of amorphous tissue. A poly-Si thin-film solar cell fabricated using this film as an active layer demonstrated a total area conversion efficiency of 9.2% (active area efficiency: 9.7%), which is the world's highest value for crystalline silicon solar cells fabricated below 600°C on metal substrates.

Chemical dry etching of silicon nitride and silicon dioxide using CF4/O2/N2 gas mixtures

Abstract: The chemical dry etching of silicon nitride (Si3N4)and silicon nitride (SiO2) in a downstream plasma reactor using CF4, O2, and N2 has been investigated. A comparison of the Si3N4 and SiO2 etch rates with that of polycrystalline silicon shows that the etch rates of Si3N4 and SiO2 are not limited by the amount of fluorine arriving on the surface only. Adding N2 in small amounts to a CF4/O2 microwave discharge increases the Si3N4 etch rate by a factor of 7, but leaves the SiO2 etch rate unchanged. This enables etch rate ratios of Si3N4 over SiO2 of 10 and greater. The Si3N4 etch rate was investigated with respect to dependence of tube length, tube geometry, and lining materials. Argon actinometry has shown that the production of F atoms in the plasma is not influenced by the addition of N2 to the discharge. Mass spectrometry shows a strong correlation between the Si3N4 etch rate and the NO concentration. X‐ray photoelectron spectra of the silicon nitride samples obtained immediately after the etching proces...

Process for the manufacture of a micromechanical element

Abstract: of EP0732635A micro-mechanical component is cut out from a base plate (20) made of a first crystalline material by anisotropic attack. This process takes effect in the direction of the thickness of the plate using a gas excited by plasma, surrounding a mask (30) of the required shape mounted above the plate. This first material may be either mono-crystalline or polycrystalline silicon or its oxide or its nitride. The parts of the component which are intended to come into contact with another component are re-coated by chemical deposition from the vapour phase with a second material. The second material is chosen to offer suitable coefficients of hardness and wear resistance for their task. The second material may, for example, be crystalline carbon in the form of diamond.

Degradation of oxynitride gate dielectric reliability due to boron diffusion

Abstract: In this letter, we report on the impact of the suppression of boron diffusion via nitridation of SiO2 on gate oxide integrity and device reliability SiO2 subjected to rapid thermal nitridation in pure nitric oxide (NO) is used to fabricate thin oxynitride gate dielectrics Both n+ polycrystalline silicon (polysilicon) gated n‐MOS (metal–oxide semiconductor) and p+‐polysilicon gated p‐MOS devices were subjected to anneals of different times to study the effect of dopant diffusion on gate oxide integrity As expected, an advanced oxynitride gate dielectric will effectively alleviate the boron‐penetration‐induced flatband voltage instability in p+‐polysilicon gated p‐MOS capacitors due to the superior diffusion barrier properties However, such improvements are observed in conjunction with some degradation of the oxide reliability due to the boron‐blocking/accumulation inside the gate dielectric Results show that even though the oxide quality is slightly degraded for NO‐nitrided SiO2 with p+‐polysilicon ga

Semiconductor device wiring or electrode

Abstract: A MOSFET in which the gate electrode is formed of a polycrystalline silicon film, a silicon nitride film having a nitrogen surface density of lens than 8×10 14 cm -2 , and a tungsten film--these films formed one upon another in the order mentioned. The gate electrode thus formed, serves to shorten the delay time of the MOSFET.

Low‐loss polycrystalline silicon waveguides for silicon photonics

Abstract: Photonic integrated circuits in silicon require waveguiding through a material compatible with silicon very large scale integrated circuit technology. Polycrystalline silicon (poly‐Si), with a high index of refraction compared to SiO2 and air, is an ideal candidate for use in silicon optical interconnect technology. In spite of its advantages, the biggest hurdle to overcome in this technology is that losses of 350 dB/cm have been measured in as‐deposited bulk poly‐Si structures, as against 1 dB/cm losses measured in waveguides fabricated in crystalline silicon. We report methods for reducing scattering and absorption, which are the main sources of losses in this system. To reduce surface scattering losses we fabricate waveguides in smooth recrystallized amorphous silicon and chemomechanically polished poly‐Si, both of which reduce losses by about 40 dB/cm. Atomic force microscopy and spectrophotometry studies are used to monitor surface roughness, which was reduced from an rms value of 19–20 nm down to ab...

Method for depositing doped amorphous or polycrystalline silicon on a substrate

Abstract: A method for forming an in-situ doped amorphous or polycrystalline silicon thin film on a substrate is provided. The method includes placing the substrate in a reaction chamber of a CVD reactor and introducing a silicon gas species into the reaction chamber. The flow of the silicon gas species is continued for a time period sufficient to dehydrate the substrate and form a thin layer of silicon. Following formation of the thin layer of silicon, a dopant gas species is introduced into the reaction chamber and continued with the flow of the silicon gas species to form the doped silicon thin film. In an illustrative embodiment a phosphorus doped amorphous silicon thin film for a cell plate of a semiconductor capacitor is formed in a LPCVD reactor.

Vibrating disk type micro-gyroscope

Abstract: A vibrating disk type micro-gyroscope and a method of manufacture thereof are disclosed. The micro-gyroscope includes a support platform for supporting a vibrating disk, the vibrating disk converting a resonance frequency into two beat frequencies, a bottom detection electrode for detecting the angular velocity of the gyroscope from a detection of the electrostatic capacitance changes between the bottom detection electrode and the vibrating disk, and an upper drive electrode for exciting the vibrating disk. The method includes the steps of: depositing an insulator layer, a polycrystalline silicon layer, the bottom detection layer, and the bottom sacrificial layer; dry etching the bottom sacrificial layer; depositing polycrystalline silicon doped with dopants; dry etching every area except the support platform and the vibrating disk; depositing an oxide upper sacrificial layer; and forming a pattern and then wet etching the upper sacrificial layer and the bottom sacrificial layer.

Hydrogen migration in polycrystalline silicon.

Abstract: Hydrogen migration in solid-state crystallized and low-pressure chemical-vapor-deposited (LPCVD) polycrystalline silicon (poly-Si) was investigated by deuterium diffusion experiments. The concentration profiles of deuterium, introduced into the poly-Si samples either from a remote D plasma or from a deuterated amorphous-silicon layer, were measured as a function of time and temperature. At high deuterium concentrations the diffusion was dispersive depending on exposure time. The dispersion is consistent with multiple trapping within a distribution of hopping barriers. The data can be explained by a two-level model used to explain diffusion in hydrogenated amorphous silicon. The energy difference between the transport level and the deuterium chemical potential was found to be about 1.2--1.3 eV. The shallow levels for hydrogen trapping are about 0.5 eV below the transport level, while the deep levels are about 1.5--1.7 eV below. The hydrogen chemical potential ${\mathrm{\ensuremath{\mu}}}_{\mathrm{H}}$ decreases as the temperature increases. At lower concentrations, ${\mathrm{\ensuremath{\mu}}}_{\mathrm{H}}$ was found to depend markedly on the method used to prepare the poly-Si, a result due in part to the dependence of crystallite size on the deposition process. Clear evidence for deuterium deep traps was found only in the solid-state crystallized material. The LPCVD-grown poly-Si, with columnar grains extending through the film thickness, displayed little evidence of deep trapping, and exhibited enhanced D diffusion. Many concentration profiles in the columnar LPCVD material indicated complex diffusion behavior, perhaps reflecting spatial variations of trap densities, complex formation, and/or multiple transport paths. Many aspects of the diffusion in poly-Si are consistent with diffusion data obtained in amorphous silicon. \textcopyright{} 1996 The American Physical Society.

Losses in polycrystalline silicon waveguides

Abstract: The losses of polycrystalline silicon (polySi) waveguides clad by SiO2 are measured by the cutback technique. We report losses of 34 dB/cm at a wavelength of 1.55 μm in waveguides fabricated from chemical mechanical polished polySi deposited at 625 °C. These losses are two orders of magnitude lower than reported absorption measurements for polySi. Waveguides fabricated from unpolished polySi deposited at 625 °C exhibit losses of 77 dB/cm. We find good agreement between calculated and measured losses due to surface scattering.

Method for manufacturing salicide semiconductor device

Abstract: In a method for manufacturing a salicide MOS device, a gate insulating layer and a polycrystalline silicon gate electrode layer are formed on a monocrystalline silicon substrate. A sidewall insulating layer is formed on a sidewall of the gate electrode layer, and impurities are introduced into the substrate with a mask of the sidewall insulating layer and the gate electrode layer, thus forming impurity diffusion regions in the substrate. Then, an upper portion of the gate electrode layer is etched out. Finally, a metal layer is formed on the entire surface, and a heating operation is carried out, so that metal silicide layers are formed on upper portions of the gate electrodes and the impurity diffusion regions. In an alternative embodiment, the gate further comprises an intervening metal nitride layer.

Method to fabricate the thin film transistor

Abstract: Ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems are used in a method which can fabricate polycrystalline silicon (poly-Si) and polycrystalline silicon-germanium (poly-Si1-x -Gex) thin film transistors at low temperature and low thermal budget. Poly-Si and poly-Si1-x -Gex can be deposited by UHV/CVD without any anneal step. And due to the ultra low base pressure and ultraclean growth environment, the As-deposited poly films have low defect densities. However, the surface morphology retards the usage of the fabricating top-gate poly TFT's. In this invention, the CMP system is used for improving the surface morphology, high performance poly-Si and poly-Si1-x -Gex TFT's can be obtained.

Nonvolatile semiconductor memory device

Abstract: PURPOSE:To obtain a large area floating gate composed of only one layer of a polycrystalline silicon layer by a method wherein a drain region and a source region are formed near a silicon substrate surface including the part of the substrate surface under an insulating film connected to a gate insulating film. CONSTITUTION:A drain region 17 which is to be a bit line for memory transistors M1 and M2 and a source region 18 which is to be a source line of the memory transistors M1 and M2 are formed as buried diffused regions. With this process, a source diffused layer 18 and a drain diffused layer 17 are extended onto the drain region 17 and the source region 18 without cutting off not only a main bit line 11, a main source line and a cell isolation region which makes cells independent from each other but also a polycrystalline silicon layer which is to be a floating gate 15. With this constitution, the source/drain and the floating gate can be formed in a self-alignment manner and, further, a large area floating gate composed of only one layer of a polycrystalline silicon layer can be obtained.

Static-induction transistors having heterojunction gates and methods of forming same

Abstract: A semiconductor switching device includes a plurality of adjacent heterojunction-gate static-induction transistor (SIT) unit cells connected in parallel in a monocrystalline silicon carbide substrate having first and second opposing faces, a relatively highly doped silicon carbide drain region adjacent the first face and a relatively highly doped silicon carbide source region adjacent the second face. A relatively lightly doped drift region is also provided in the substrate and extends between the drain region and source region. A plurality of trenches are also provided in the substrate so that sidewalls of the trenches extend adjacent the drift region. Each trench preferably contains a relatively highly doped second conductivity type nonmonocrystalline silicon gate region comprised of a material selected from the group consisting of polycrystalline silicon or amorphous silicon. These gate regions form P-N heterojunctions with the drift region at the sidewalls and bottoms of the trenches. An electrically insulating layer, such as a thermally grown silicon dioxide layer, is also provided on the nonmonocrystalline silicon gate regions in order to electrically insulate the gate regions from metallization on the second face. The use of nonmonocrystalline materials for the gate regions is preferred because the nonmonocrystalline lattice structure of the gate regions provides numerous grain boundaries and other lattice defects which act as scattering sites for electrons. By providing scattering sites, the probability that accelerated electrons will reach the threshold energy to induce avalanche breakdown in the gate regions is reduced and an increase in forward blocking voltage capability is achieved. Hole injection from the P+ polycrystalline silicon gate region into the N-type drift can also be suppressed to significantly improve the switching speed by reducing the amount of stored charge in the drift region.

Inverse staggered poly-Si and amorphous Si double structure TFT's for LCD panels with peripheral driver circuits integration

Abstract: Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300/spl deg/C, Ar/sup +/ and XeCl (300 mJ/cm/sup 2/) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n/sup +/ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm /sup 2//V/spl middot/s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively.

Process and apparatus for manufacturing polycrystalline silicon, and process for manufacturing silicon wafer for solar cell

Abstract: An object of the present invention is to provide a process and apparatus for the continuous flow production of polycrystalline silicon from metallic silicon or silicon oxide as a raw material and also for the manufacture of a wafer by using it, which process and apparatus permit the mass production at a low cost. The above object can be attained by the manufacture of polycrystalline silicon and a silicon wafer for a solar cell by the following steps: (A) smelting metallic silicon under reduced pressure, carrying out solidification for the removal of the impurity components from the melt, thereby obtaining a first ingot, (B) removing the impurity concentrated portion from the ingot by cutting, (C) re-melting the remaining portion, removing boron and carbon from the melt by oxidizing under an oxidizing atmosphere, and blowing a mixed gas of argon and water to carry out deoxidization, (D) casting the deoxidized melt into a mold, and carried out directional solidification to obtain a second ingot, and (E) removing the impurity concentrated portion of the ingot obtained by directional solidification by cutting.

Deep trench filling method using silicon film deposition and silicon migration

Abstract: A method of filling one or more trenches formed in a silicon substrate includes the steps of forming a thin polycrystalline silicon film in a trench such that the thin polycrystalline silicon film is sufficiently thin so as to not close the trench; forming an amorphous silicon film on thin polycrystalline film and the surface of the substrate and in the trenches; and annealing the amorphous silicon film such that the amorphous silicon layer migrates to fill the trenches to a first level. The deposition and annealing steps are performed in ambient atmospheres having low partial pressures of H 2 O and O 2 , the annealing temperature is higher than the deposition temperature, and the annealing pressure is greater than the deposition pressure.

Tensile Testing of Polycrystalline Silicon Thin Films Using Electrostatic Force Grip.

Abstract: In this paper, a new tensile tester for thin films is presented. This tensile tester has a grip that fixes a thin film specimen using electrostatic force. The tester was constructed in a scanning electron microscope (SEM) chamber. Using this tester, the tensile strengths of polycrystalline silicon (poly-Si) thin films have been measured. The tested part of the specimen is 30-300μm long, 5μm wide and 2μm thick. The fracture of the poly-Si thin film was brittle. The mean tensile strength was 2.0-2.6GPa, depending on the length of the tested part. The size of the critical flaw that initiates fracture of the poly-Si thin film is 28-47nm, rather small than the grain size of the poly-Si thin film.

High‐resolution silicon patterning with self‐assembled monolayer resists

Abstract: Single crystal and polycrystalline silicon films have been patterned and etched with a novel high‐selectivity process using self‐assembled monolayer resists of octadecylsiloxanes (ODS). The highest resolution patterning of sub‐10 nm features has been demonstrated by scanning force microscopy imaging of ODS layers patterned with a focused electron beam. An all‐dry UV/ozone developer has been used to remove residual carbon from the electron beam exposed regions to improve etch selectivity. The positive tone pattern transfer process consisted of a short buffered hydrofluoric acid wet etch to remove the silicon native oxide followed by a high‐selectivity, low ion energy etch using Cl2 and BCl3 in an electron cyclotron resonance reactive ion etch. Features have been etched up to 90 nm deep into Si(100) wafers and minimum feature sizes obtained are ∼25 nm. Poly‐Si films on SiO2 insulator layers have been similarly patterned and have been used in a combined process with photolithographic definition of microbridg...

On the threshold voltage and channel conductance of polycrystalline silicon thin‐film transistors

Abstract: A model for the grain‐boundary barrier height of undoped polycrystalline silicon thin‐film transistors is developed based on a rodlike structure of the grains with a square cross section and a Gaussian energy distribution of the trapping states at the grain boundaries. An analytical expression for the threshold voltage is derived in terms of the distribution parameters of the grain‐boundary trapping states, the grain size, and the gate oxide thickness. Comparison between the developed model and the experimental drain current versus gate voltage data has been made and excellent agreement was obtained. The key parameters affecting the threshold voltage and the channel conductance of the transistor were investigated by computer stimulation. The threshold voltage is mainly affected by the grain size and the gate oxide thickness. For the improvement of the channel conductance, besides the passivation of the grain‐boundary trapping states, the increase of the grain size and mainly the scaling down of the gate o...

Method for forming high resistance resistors for limiting cathode current in field emission displays

Abstract: A method for forming resistors for regulating current in a field emission display (10) comprises integrating a high resistance resistor (32) into circuitry for the field emission display The resistor (32) is in electrical communication with emitter sites (14) for the field emission display (10) and with other circuit components such as ground The high resistance resistor (32) can be formed as a layer of a high resistivity material, such as intrinsic polycrystalline silicon, polycrystalline silicon doped with a conductivity-degrading dopant, lightly doped polysilicon, titanium oxynitride, tantalum oxynitride or a glass type material deposited on a baseplate (12) of the field emission display (10) Contacts (38, 39) are formed in the high resistivity material to establish electrical communication between the resistor (32) and the emitter sites (14) and between the resistor (32) and the other circuit components The contacts (38, 39) can be formed as low resistance contacts (eg, ohmic contacts) or as high resistance contacts (eg, Schottky contacts)

Polycrystalline silicon formation by pulsed rapid thermal annealing of amorphous silicon

Abstract: A method of forming polycrystalline silicon (polysilicon) from amorphous silicon in several seconds is presented in this letter. This solid‐phase crystallization process was carried out with the pulsed rapid thermal annealing method using a metal as the seed. The crystal‐growth process was monitored with an optical microscope and the polysilicon structure was confirmed by a micro‐Raman shift measurement. Polysilicon film within a 30‐micrometer channel was formed using 3 pulses of 1‐s 800 °C heating/5‐s cooling. It took more than 13 h using a 500 °C furnace annealing method to form polysilicon film within a 12‐micrometer channel. Since the substrate is only exposed to the high temperature for a very short period of time, heat effects in the substrate are minimized. This method has the potential for use in the fabrication of small geometry devices, such as thin film transistors, on large‐area, low temperature glass substrates.

Mechanical properties of thick, surface micromachined polysilicon films

Abstract: Polycrystalline silicon is the most widely used structural material for surface micromachined microelectromechanical systems (MEMS) There are many advantages to using thick polysilicon films; however, due to process equipment limitations, these devices are typically fabricated from polysilicon films less than 3 /spl mu/m thick In this work, microelectromechanical test structures were designed and processed from thick (up to 10 /spl mu/m) undoped and in situ boron-doped polysilicon films The elastic moduli of the doped films were 150/spl plusmn/30 GPa, and appeared to be independent of film thickness The thermal oxidation of the polysilicon induced a compressive stress into the top surface of the films, which was detected as a residual stress in the polysilicon after the device fabrication was complete The average nominal fracture toughness of the polysilicon was 23/spl plusmn/01 MPa /spl radic/m

Method for preparing molten silicon melt from polycrystalline silicon charge

Abstract: A method and apparatus for preparing molten silicon melt from polycrystalline silicon in a crystal pulling apparatus entails loading an amount of polycrystalline silicon loaded into the crucible less than a predetermined total amount of polycrystalline silicon to be melted. The crucible is heated to form a partially melted charge in the crucible having an island of unmelted polycrystalline silicon exposed above an upper surface of melted silicon. Granular polycrystalline silicon is fed from a feeder onto the island of unmelted polycrystalline silicon until the predetermined total amount of polycrystalline silicon has been loaded into the crucible. The position of the island relative to the crucible side wall is electronically determined as granular polycrystalline silicon is fed onto the island. The feed rate at which granular polycrystalline silicon is fed from the feeder onto the island of unmelted polycrystalline silicon is controlled in response to the determined position of the island relative to the crucible side wall.

High-performance thin-film transistors in large grain size polysilicon deposited by thermal decomposition of disilane

Abstract: The characteristics of polycrystalline silicon thin-film transistors (TFTs), fabricated on films deposited in an LPCVD system using disilane, were investigated as a function of grain size. The grain size and its statistical distribution were correlated with processing conditions; optimum conditions to maximize grain size for device applications were determined. The dependence of the ON current and the OFF (leakage) current of polysilicon TFTs, as well as of their statistical distributions, on the grain size, the gate dielectric processing temperature, the channel length, and the device structure are reported and discussed. Larger grain size polycrystalline silicon films were found to yield devices with higher mobilities and lower leakage currents. TFTs, fabricated in polysilicon films with average grain sizes of 1.8 /spl mu/m with thermally grown silicon dioxide as gate dielectric, had ON/OFF current ratio well above 10/sup 8/, average effective mobility value of 170 cm/sup 2//V.s and subthreshold slope of 0.3 V/dec.