Showing papers on "Substrate (electronics) published in 2012"

Large-area vapor-phase growth and characterization of MoS(2) atomic layers on a SiO(2) substrate.

Abstract: Atomic-layered MoS(2) is synthesized directly on SiO(2) substrates by a scalable chemical vapor deposition method. The large-scale synthesis of an atomic-layered semiconductor directly on a dielectric layer paves the way for many facile device fabrication possibilities, expanding the important family of useful mono- or few-layer materials that possess exceptional properties, such as graphene and hexagonal boron nitride (h-BN).

Gallium oxide (Ga2O3) metal-semiconductor field-effect transistors on single-crystal β-Ga2O3 (010) substrates

Abstract: We report a demonstration of single-crystal gallium oxide (Ga2O3) metal-semiconductor field-effect transistors (MESFETs). A Sn-doped Ga2O3 layer was grown on a semi-insulating β-Ga2O3 (010) substrate by molecular-beam epitaxy. We fabricated a circular MESFET with a gate length of 4 μm and a source–drain spacing of 20 μm. The device showed an ideal transistor action represented by the drain current modulation due to the gate voltage (VGS) swing. A complete drain current pinch-off characteristic was also obtained for VGS < −20 V, and the three-terminal off-state breakdown voltage was over 250 V. A low drain leakage current of 3 μA at the off-state led to a high on/off drain current ratio of about 10 000. These device characteristics obtained at the early stage indicate the great potential of Ga2O3-based electrical devices for future power device applications.

Highly Conductive and Transparent PEDOT:PSS Films with a Fluorosurfactant for Stretchable and Flexible Transparent Electrodes

Abstract: Highly conductive and transparent poly-(3,4-ethylenedioxythiophene):poly(styrenesulfonic acid) (PEDOT:PSS) films, incorporating a fluorosurfactant as an additive, have been prepared for stretchable and transparent electrodes. The fluorosurfactant-treated PEDOT:PSS films show a 35% improvement in sheet resistance (Rs) compared to untreated films. In addition, the fluorosurfactant renders PEDOT:PSS solutions amenable for deposition on hydrophobic surfaces, including pre-deposited, annealed films of PEDOT:PSS (enabling the deposition of thick, highly conductive, multilayer films) and stretchable poly(dimethylsiloxane) (PDMS) substrates (enabling stretchable electronics). Four-layer PEDOT:PSS films have an Rs of 46 Ω per square with 82% transmittance (at 550 nm). These films, deposited on a pre-strained PDMS substrate and buckled, are shown to be reversibly stretchable, with no change to Rs, during the course of over 5000 cycles of 0 to 10% strain. Using the multilayer PEDOT:PSS films as anodes, indium tin oxide (ITO)-free organic photovoltaics are prepared and shown to have power conversion efficiencies comparable to that of devices with ITO as the anode. These results show that these highly conductive PEDOT:PSS films can not only be used as transparent electrodes in novel devices (where ITO cannot be used), such as stretchable OPVs, but also have the potential to replace ITO in conventional devices.

Advances in 2D boron nitride nanostructures: nanosheets, nanoribbons, nanomeshes, and hybrids with graphene

Abstract: The recent surge in graphene research has stimulated interest in the investigation of various 2-dimensional (2D) nanomaterials. Among these materials, the 2D boron nitride (BN) nanostructures are in a unique position. This is because they are the isoelectric analogs to graphene structures and share very similar structural characteristics and many physical properties except for the large band gap. The main forms of the 2D BN nanostructures include nanosheets (BNNSs), nanoribbons (BNNRs), and nanomeshes (BNNMs). BNNRs are essentially BNNSs with narrow widths in which the edge effects become significant; BNNMs are also variations of BNNSs, which are supported on certain metal substrates where strong interactions and the lattice mismatch between the substrate and the nanosheet result in periodic shallow regions on the nanosheet surface. Recently, the hybrids of 2D BN nanostructures with graphene, in the form of either in-plane hybrids or inter-plane heterolayers, have also drawn much attention. In particular, the BNNS–graphene heterolayer architectures are finding important electronic applications as BNNSs may serve as excellent dielectric substrates or separation layers for graphene electronic devices. In this article, we first discuss the structural basics, spectroscopic signatures, and physical properties of the 2D BN nanostructures. Then, various top-down and bottom-up preparation methodologies are reviewed in detail. Several sections are dedicated to the preparation of BNNRs, BNNMs, and BNNS–graphene hybrids, respectively. Following some more discussions on the applications of these unique materials, the article is concluded with a summary and perspectives of this exciting new field.

A III–V nanowire channel on silicon for high-performance vertical transistors

Abstract: The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.

The Nature of Electronic States in Atomically Thin MoS2 Field-Effect Transistors

Abstract: We present low temperature electrical transport experiments in five field effect transistor devices consisting of monolayer, bilayer and trilayer MoS2 films, mechanically exfoliated onto Si/SiO2 substrate. Our experiments reveal that the electronic states in all films are localized well up to the room temperature over the experimentally accessible range of gate voltage. This manifests in two dimensional (2D) variable range hopping (VRH) at high temperatures, while below \sim 30 K the conductivity displays oscillatory structures in gate voltage arising from resonant tunneling at the localized sites. From the correlation energy (T0) of VRH and gate voltage dependence of conductivity, we suggest that Coulomb potential from trapped charges in the substrate are the dominant source of disorder in MoS2 field effect devices, which leads to carrier localization as well.

Semiconductor device and method of fabricating the same

Abstract: A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.

Ultra-thin perfect absorber employing a tunable phase change material

Abstract: We show that perfect absorption can be achieved in a system comprising a single lossy dielectric layer of thickness much smaller than the incident wavelength on an opaque substrate by utilizing the nontrivial phase shifts at interfaces between lossy media. This design is implemented with an ultra-thin (∼λ/65) vanadium dioxide (VO2) layer on sapphire, temperature tuned in the vicinity of the VO2 insulator-to-metal phase transition, leading to 99.75% absorption at λ = 11.6 μm. The structural simplicity and large tuning range (from ∼80% to 0.25% in reflectivity) are promising for thermal emitters, modulators, and bolometers.

Synthesis and Characterization of Hexagonal Boron Nitride Film as a Dielectric Layer for Graphene Devices

Abstract: Hexagonal boron nitride (h-BN) is a promising material as a dielectric layer or substrate for two-dimensional electronic devices. In this work, we report the synthesis of large-area h-BN film using atmospheric pressure chemical vapor deposition on a copper foil, followed by Cu etching and transfer to a target substrate. The growth rate of h-BN film at a constant temperature is strongly affected by the concentration of borazine as a precursor and the ambient gas condition such as the ratio of hydrogen and nitrogen. h-BN films with different thicknesses can be achieved by controlling the growth time or tuning the growth conditions. Transmission electron microscope characterization reveals that these h-BN films are polycrystalline, and the c-axis of the crystallites points to different directions. The stoichiometry ratio of boron and nitrogen is close to 1:1, obtained by electron energy loss spectroscopy. The dielectric constant of h-BN film obtained by parallel capacitance measurements (25 μm2 large areas) ...

Planar superconducting resonators with internal quality factors above one million

Abstract: We describe the fabrication and measurement of microwave coplanar waveguide resonators with internal quality factors above 107 at high microwave powers and over 106 at low powers, with the best low power results approaching 2×106, corresponding to ∼1 photon in the resonator. These quality factors are achieved by controllably producing very smooth and clean interfaces between the resonators’ aluminum metallization and the underlying single crystal sapphire substrate. Additionally, we describe a method for analyzing the resonator microwave response, with which we can directly determine the internal quality factor and frequency of a resonator embedded in an imperfect measurement circuit.

Layered boron nitride as a release layer for mechanical transfer of GaN-based devices

Abstract: Introducing an extremely thin layer of boron nitride between a sapphire substrate and the gallium nitride semiconductor grown on it is shown to facilitate the transfer of the resulting nitride structures to more flexible and affordable substrates. Nitride semiconductors are renowned for their excellent electronic and optical properties and are the materials of choice for many optical devices, including BluRay players. But they have an important practical drawback: they are very particular about the substrates (typically sapphire) on which they can be grown. This has stimulated the search for new ways of transferring such materials from one substrate to another. Here Kobayashi et al. demonstrate, using a gallium nitride-based device, that the addition of an extremely thin layer of hexagonal boron nitride to the initial growth surface facilitates the straightforward mechanical release of the resulting nitride structures, as well as subsequent transfer to any suitable substrate, including metals, glass and transparent plastics. Nitride semiconductors are the materials of choice for a variety of device applications, notably optoelectronics1,2 and high-frequency/high-power electronics3. One important practical goal is to realize such devices on large, flexible and affordable substrates, on which direct growth of nitride semiconductors of sufficient quality is problematic. Several techniques—such as laser lift-off4,5—have been investigated to enable the transfer of nitride devices from one substrate to another, but existing methods still have some important disadvantages. Here we demonstrate that hexagonal boron nitride (h-BN) can form a release layer that enables the mechanical transfer of gallium nitride (GaN)-based device structures onto foreign substrates. The h-BN layer serves two purposes: it acts as a buffer layer for the growth of high-quality GaN-based semiconductors, and provides a shear plane that makes it straightforward to release the resulting devices. We illustrate the potential versatility of this approach by using h-BN-buffered sapphire substrates to grow an AlGaN/GaN heterostructure with electron mobility of 1,100 cm2 V−1 s−1, an InGaN/GaN multiple-quantum-well structure, and a multiple-quantum-well light-emitting diode. These device structures, ranging in area from five millimetres square to two centimetres square, are then mechanically released from the sapphire substrates and successfully transferred onto other substrates.

Growth of silicene layers on Ag(111): unexpected effect of the substrate temperature

Abstract: The deposition of one silicon monolayer on the silver (111) substrate in the temperature range 150-300 °C gives rise to a mix of (4 × 4), (2√3 × 2√3)R30° and (√13 × √13)R13.9° superstructures which strongly depend on the substrate temperature. We deduced from a detailed analysis of the LEED patterns and the STM images that all these superstructures are given by a quasi-identical silicon single layer with a honeycomb structure (i.e. a silicene-like layer) with different rotations relative to the silver substrate. The morphologies of the STM images are explained from the position of the silicon atoms relative to the silver atoms. A complete analysis of all possible rotations of the silicene layer predicts also a (√7 × √7)R19.1° superstructure which has not been observed so far.

Apparatus and method for forming semiconductor contacts

Abstract: A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.

Ultrahigh-density array of silver nanoclusters for SERS substrate with high sensitivity and excellent reproducibility.

Abstract: We introduce a simple but robust method to fabricate an ultrahigh-density array of silver nanoclusters for a surface-enhanced Raman spectroscopy (SERS) substrate with high sensitivity and excellent reproducibility at a very large area (wafer scale) based on polystyrene-block-poly(4-vinylpyridine) copolymer (PS-b-P4VP) micelles. After silver nitrates were incorporated into the micelle cores (P4VP) followed by the reduction to silver nanoclusters, we systematically controlled the gap distance between two neighboring silver nanoclusters ranging from 8 to 61 nm, while the diameter of each silver nanocluster was kept nearly constant (∼25 nm). To make a silver nanocluster array with a gap distance of 8 nm, the use of crew-cut-type micelles is required. Fabricated SERS substrate with a gap distance of 8 nm showed very high signal intensity with a SERS enhancement factor as high as 108, which is enough to detect a single molecule, and excellent reproducibility (less than ±5%) of the signal intensity. This is beca...

Semiconductor light emitting device

Abstract: The present invention relates to a semiconductor light-emitting device. The semiconductor light-emitting device comprises: a substrate; an n-type semiconductor layer for providing electrons when voltage is applied thereto; a p-type semiconductor layer for providing electron holes when voltage is applied thereto; a conductive n-type electrode for applying voltage to the n-type semiconductor layer; a conductive p-type electrode for applying voltage to the p-type semiconductor layer; an active layer which is interposed between the n-type semiconductor layer and the p-type semiconductor layer, and which has a quantum well structure for activating electron-hole combination; and a current-spreading and hole injection layer which is interposed between the p-type semiconductor layer and the p-type electrode, and in which both an n-type impurity and a p-type impurity are doped together for current-spreading and hole injection between the p-type electrode and the p-type semiconductor layer. Consequently, the semiconductor light-emitting device of the present invention is advantageous in that it not only reduces contact resistance between an electrode and a semiconductor layer, improving current flow and rendering current-spreading further uniform, but also improves hole injection performance, thereby achieving the maximized efficiency of the device.

Light-Emitting Two-Dimensional Ultrathin Silicon Carbide

Abstract: Two-dimensional (2D) atomic crystals, especially graphene, have received much attention. However, the main shortcoming of graphene is its zero band gap. Silicon carbide, composed of silicon and carbon, is a typical wurtzite compound semiconductor, with more than 250 alloy types. Herein, we give some evidence of the solution exfoliation of 2D SiC nanoflakes with thickness down to 0.5–1.5 nm. Transmission electron microscopy (TEM) and X-ray diffraction characterizations reveal that graphitic (0001)/(0001) SiC most possibly has been formed by sonication of wurtzite SiC. Graphene, which is also produced in this process, naturally forms the ultrathin substrate facilitating the TEM characterization of 2D SiC. The mechanism of this exfoliation process should be related to the surface reconstruction of wurtzite SiC into graphitic SiC. Photoluminescence spectra show a strong light-emitting ability and a quantum-confinement-induced emission peak at 373 nm for these ultrathin SiC nanosheets.

Wafer-scale integration of group III – V lasers on silicon using transfer printing of epitaxial layers

Abstract: The realization of GaAs lasers on a silicon substrate using a print transfer process offers an alternative wafer-bonding technique for the hybrid integration of optoelectronics.

Polycrystalline Silicon for Integrated Circuits and Displays

Abstract: Polycrystalline Silicon for Integrated Circuits and Displays, Second Edition presents much of the available knowledge about polysilicon. It represents an effort to interrelate the deposition, properties, and applications of polysilicon. By properly understanding the properties of polycrystalline silicon and their relation to the deposition conditions, polysilicon can be designed to ensure optimum device and integrated-circuit performance. Polycrystalline silicon has played an important role in integrated-circuit technology for two decades. It was first used in self-aligned, silicon-gate, MOS ICs to reduce capacitance and improve circuit speed. In addition to this dominant use, polysilicon is now also included in virtually all modern bipolar ICs, where it improves the basic physics of device operation. The compatibility of polycrystalline silicon with subsequent high-temperature processing allows its efficient integration into advanced IC processes. This compatibility also permits polysilicon to be used early in the fabrication process for trench isolation and dynamic random-access-memory (DRAM) storage capacitors. In addition to its integrated-circuit applications, polysilicon is becoming vital as the active layer in the channel of thin-film transistors in place of amorphous silicon. When polysilicon thin-film transistors are used in advanced active-matrix displays, the peripheral circuitry can be integrated into the same substrate as the pixel transistors. Recently, polysilicon has been used in the emerging field of microelectromechanical systems (MEMS), especially for microsensors and microactuators. In these devices, the mechanical properties, especially the stress in the polysilicon film, are critical to successful device fabrication. Polycrystalline Silicon for Integrated Circuits and Displays, Second Edition is an invaluable reference for professionals and technicians working with polycrystalline silicon in the integrated circuit and display industries.

Origin of doping in quasi-free-standing graphene on silicon carbide.

Abstract: We explain the robust p-type doping observed for quasi-free-standing graphene on hexagonal silicon carbide by the spontaneous polarization of the substrate. This mechanism is based on a bulk property of SiC, unavoidable for any hexagonal polytype of the material and independent of any details of the interface formation. We show that sign and magnitude of the polarization are in perfect agreement with the doping level observed in the graphene layer. With this mechanism, models based on hypothetical acceptor-type defects as they are discussed so far are obsolete. The n-type doping of epitaxial graphene is explained conventionally by donorlike states associated with the buffer layer and its interface to the substrate that overcompensate the polarization doping. The basis for the unique electronic and optical properties of graphene is the linear dispersion relation of the � electrons, which is responsible for Dirac-type quasiparticles with many unusual properties. The band structure in the relevant energy range is made up by double cones in the corners of the two-dimensional hexagonal Brillouin zone; their opening angle is determined by the slope vF ¼ d! dk of the dispersion relation called the Fermi velocity, which is an intrinsic material parameter. The origin of these so-called Dirac cones defines the Fermi energy in an isolated and intrinsic graphene layer. At finite temperatures, the reservoir of mobile charge carriers is due to thermal excitation of equal concentrations n0 and p0 of electrons and holes. Evaluation of the Fermi statistics yields a value of n0 ¼ �k 2 B

Polymeric material with metal-like conductivity for next generation organic electronic devices

Abstract: The reduced pressure synthesis of poly(3,4-ethylenedioxythiophene) (PEDOT) with sheet-like morphology has been achieved with the introduction of an amphiphilic triblock copolymer into the oxidant thin film. Addition of the copolymer not only results in an oxidant thin film which remains liquid-like under reduced pressure but also induces structured growth during film formation. PEDOT films were polymerized using the vacuum vapor phase polymerization (VPP) technique, in which we show that maintaining a liquid-like state for the oxidant is essential. The resulting conductivity is equivalent to commercially available indium tin oxide (ITO) with concomitant optical transmission values. PEDOT films can be produced with a variety of thicknesses across a range of substrate materials from plastics to metals to ceramics, with sheet resistances down to 45 Ω/□ (ca. 3400 S·cm–1), and transparency in the visible spectrum of >80% at 65 nm thickness. This compares favorably to ITO and its currently touted replacements.

Patterning by controlled cracking

Abstract: Propagating cracks—normally associated with material failure and viewed as undesirable—can be controlled in a film/substrate system, opening up new possibilities for nanofabrication and atomic-scale patterning. Crack propagation is usually associated with materials failure, and as such is to be avoided. In the right place, however, crack formation can be useful. A team based in South Korea has developed a technique that harnesses crack initiation, propagation and termination to create patterns in a silicon nitride thin film deposited on top of a silicon substrate. Nam et al. introduce into the substrate notches that concentrate stress to initiate cracks spontaneously during deposition; they also define three modes of crack propagation and prepare multistep structures in the silicon substrate to terminate propagation at specific locations. They even bend cracks in a way that resembles the refraction of light. This concept opens up new possibilities for nanofabrication and patterning using fracture mechanics in applications such as nanotechnology and micro-scale fluidic devices. Crack formation drives material failure and is often regarded as a process to be avoided1,2,3. However, closer examination of cracking phenomena has revealed exquisitely intricate patterns such as spirals4, oscillating5,6,7 and branched7 fracture paths and fractal geometries8. Here we demonstrate the controlled initiation, propagation and termination of a variety of channelled crack patterns in a film/substrate system9,10,11 comprising a silicon nitride thin film deposited on a silicon substrate using low-pressure chemical vapour deposition. Micro-notches etched into the silicon substrate concentrated stress for crack initiation, which occurred spontaneously during deposition of the silicon nitride layer. We reproducibly created three distinct crack morphologies—straight, oscillatory and orderly bifurcated (stitchlike)—through careful selection of processing conditions and parameters. We induced direction changes by changing the system parameters, and we terminated propagation at pre-formed multi-step crack stops. We believe that our patterning technique presents new opportunities in nanofabrication and offers a starting point for atomic-scale pattern formation12, which would be difficult even with current state-of-the-art nanofabrication methodologies.

Layered semiconductor molybdenum disulfide nanomembrane based Schottky-barrier solar cells

Abstract: We demonstrate Schottky-barrier solar cells employing a stack of layer-structured semiconductor molybdenum disulfide (MoS2) nanomembranes, synthesized by the chemical-vapor-deposition method, as the critical photoactive layer An MoS2 nanomembrane forms a Schottky-barrier with a metal contact by the layer-transfer process onto an indium tin oxide (ITO) coated glass substrate Two vibrational modes in MoS2 nanomembranes, E12g (in-plane) and A1g (perpendicular-to-plane), were verified by Raman spectroscopy With a simple stacked structure of ITO–MoS2–Au, the fabricated solar cell demonstrates a photo-conversion efficiency of 07% for ∼110 nm MoS2 and 18% for ∼220 nm MoS2 The improvement is attributed to a substantial increase in photonic absorption The MoS2 nanomembrane exhibits efficient photo-absorption in the spectral region of 350–950 nm, as confirmed by the external quantum efficiency A sizable increase in MoS2 thickness results in only minor change in Mott–Schottky behavior, indicating that defect density is insensitive to nanomembrane thickness attributed to the dangling-bond-free layered structure

Methods for etch of metal and metal-oxide films

Abstract: A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Silicon carbide semiconductor device

Abstract: This silicon-carbide semiconductor device (101) has a silicon-carbide substrate (10), a main electrode (52), a first barrier layer (70a), and a wiring layer (60). The main electrode (52) is provided directly on top of the silicon-carbide substrate (10). The first barrier layer (70a) is provided on top of the main electrode (52) and is made from a conductive material that does not contain aluminum. The wiring layer (60) is provided on top of the first barrier layer (70a), is isolated from the main electrode (52) by the first barrier layer (70a), and is made from a material that does contain aluminum.

Self-assembled reduced graphene oxide/carbon nanotube thin films as electrodes for supercapacitors

Abstract: Graphene oxide/carbon nanotube (GO/CNT) hybrid films are self-assembled on a Ti substrate via simple casting of aqueous dispersion. The amphiphilic nature of graphene oxide sheets allows adsorption of CNTs onto their surface in water, capable of forming a highly stable dispersion. Binder-free electrodes are prepared using the annealed GO/CNT films for high performance supercapacitors. The hybrid film electrodes with a moderate CNT content, typically 12.5 wt%, give rise to remarkable electrochemical performance with extremely high specific capacitances of 428 and 145 F g−1 at current densities of 0.5 and 100 A g−1, respectively, as well as a remarkable retention rate of 98% of the initial value after 10 000 charge/discharge cycles. The synergistic effects arising from (i) the enlarged surface area of electrodes due to the intercalation of CNTs between the stacked GO sheets with associated large electrochemical active sites and (ii) the improved conductivity through the formation of a 3D network aided by CNTs are mainly responsible for these findings.

Structural, electrical, and terahertz transmission properties of VO2 thin films grown on c-, r-, and m-plane sapphire substrates

Abstract: The structure, metal-insulator transition (MIT), and related Terahertz (THz) transmission characteristics of VO2 thin films obtained by sputtering deposition on c-, r-, and m-plane sapphire substrates were investigated by different techniques. On c-sapphire, monoclinic VO2 films were characterized to be epitaxial films with triple domain structure caused by β-angle mismatch. Monoclinic VO2 β angle of 122.2° and the two angles of V4+–V4+ chain deviating from the am axis of 4.4° and 4.3° are determined. On r-sapphire, tetragonal VO2 was determined to be epitaxially deposited with VO2 (011)T perpendicular to the growth direction, while the structural phase transformation into lower symmetric monoclinic phase results in (2¯11) and (200) orientations forming a twinned structure. VO2 on m-sapphire has several growth orientations, related with the uneven substrate surface and possible inter-diffusion between film and substrate. Measurements of the electrical properties show that the sample on r-sapphire has MIT ...

High mobility flexible graphene field-effect transistors with self-healing gate dielectrics.

Abstract: A high-mobility low-voltage graphene field-effect transistor (FET) array was fabricated on a flexible plastic substrate using high-capacitance natural aluminum oxide as a gate dielectric in a self-aligned device configuration. The high capacitance of the native aluminum oxide and the self-alignment, which minimizes access resistance, yield a high current on/off ratio and an operation voltage below 3 V, along with high electron and hole mobility of 230 and 300 cm2/V·s, respectively. Moreover, the native aluminum oxide is resistant to mechanical bending and exhibits self-healing upon electrical breakdown. These results indicate that self-aligned graphene FETs can provide remarkably improved device performance and stability for a range of applications in flexible electronics.

Manufacturing method of semiconductor device

Abstract: PROBLEM TO BE SOLVED: To suppress a void from occurring in a silicon oxide film formed in a spin on dielectric (SOD) methodSOLUTION: A manufacturing method of a semiconductor device including a substrate, a groove-shaped region G formed on a surface of the substrate, and a silicon oxide film 8 buried in the groove-shaped region G comprises: a liner film formation step of forming a liner film 6 covering the surface of the substrate including the groove-shaped region G; a water-washing step of washing a surface of the liner film 6 in water; a moisture removal step of removing residual water after water washing; a coating step of coating the surface of the substrate with a polysilazane solution by spin coating; and a reforming step of reforming the polysilazane solution into the silicon oxide film 8 by annealing

Kerf-Less Removal of Si, Ge, and III–V Layers by Controlled Spalling to Enable Low-Cost PV Technologies

Abstract: Kerf-less removal of surface layers of photovoltaic materials including silicon, germanium, and III-Vs is demonstrated by controlled spalling technology. The method is extremely simple, versatile, and applicable to a wide range of substrates. Controlled spalling technology requires a stressor layer, such as Ni, to be deposited on the surface of a brittle material, and the controlled removal of a continuous surface layer could be performed at a predetermined depth by manipulating the thickness and stress of the Ni layer. Because the entire process is at room temperature, this technique can be applied to kerf-free ingot dicing, removal of preformed p-n junctions or epitaxial layers, or even completed devices. We successfully demonstrate kerf-free ingot dicing, as well as the removal of III-V single-junction epitaxial layers from a Ge substrate. Solar cells formed on the spalled and transferred single-junction layers showed similar characteristics to nonspalled (bulk) cells, indicating that the quality of the epitaxial layers is not compromised as a result of spalling.