Showing papers on "Tunnel field-effect transistor published in 2016"

Tunnel Field-Effect Transistor With an L-Shaped Gate

Abstract: In this letter, a new L-shaped gate tunnel field-effect transistor (LG-TFET) is proposed and investigated by Silvaco Atlas simulation. The tunneling junction in the LG-TFET is perpendicular to the channel direction that facilitates the implementation of a relatively large tunneling junction area. The channel is U-shaped that makes the channel mainly distribute in the vertical direction, reducing the device area. The n+ pocket design is also introduced between the source and the intrinsic regions to improve the device characteristic. In addition, the gate and n+ pocket region overlap both in the vertical and the lateral directions resulting in an enhanced electric field, and the ON-state current of the LG-TFET is increased up to $\sim 50$ % compared with the previous L-shaped channel TFET. The minimum subthreshold swing of the LG-TFET is 38.5 mV/decade at 0.2 V gate-to-source voltage. By using the L-shaped gate, U-shaped channel, and the insertion of n+ pocket, the overall performance of the LG-TFET is optimized.

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

Abstract: The implementation and operation of the nonvolatile ferroelectric memory (NVM) tunnel field effect transistors with silicon-doped HfO2 is proposed and theoretically examined for the first time, showing that ferroelectric nonvolatile tunnel field effect transistor (Fe-TFET) can operate as ultra-low power nonvolatile memory even in aggressively scaled dimensions. A Fe-TFET analytical model is derived by combining the pseudo 2-D Poisson equation and Maxwell’s equation. The model describes the Fe-TFET behavior when a time-dependent voltage is applied to the device with hysteretic output characteristic due to the ferroelectric’s dipole switching. The theoretical results provide unique insights into how device geometry and ferroelectric properties affect the Fe-TFET transfer characteristic. The recently explored ferroelectric, silicon-doped HfO2 is employed as the gate ferroelectric. With the ability to engineer ferroelectricity in HfO2 thin films, a high-K dielectric well established in memory devices, the silicon-doped HfO2 opens a new route for improved manufacturability and scalability of future 1-T ferroelectric memories. In the current research, a Si:HfO2 based Fe-TFET with large memory window and low power dissipation is designed and simulated. Utilizing our presented model, the device characteristics of a Fe-TFET that takes full benefits from Si:HfO2 is compared with the same devices using well-known perovskite ferroelectrics. Finally, the Fe-TFET is compared with a conventional ferroelectric memory transistor highlighting the advantages of using tunneling memory devices.

Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure

Abstract: Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications.

Improved Retention Time in Twin Gate 1T DRAM With Tunneling Based Read Mechanism

Abstract: We report a twin gate tunnel field effect transistor-based capacitorless dynamic memory with improved retention characteristics through well-calibrated simulations. The first front gate of the twin gate architecture regulates the read mechanism based on band-to-band tunneling whereas the second front gate creates and maintains a dedicated volume for the charge storage near the drain region. The profound well along with the optimized bias values aid to attain a retention time ( RT ) of $\sim 1.5$ s at 85 °C. Systematic analysis shows that the storage region can be scaled down to 50 nm with further improvement in RT by using an underlap region between drain and second gate. Optimally designed twin gate device exhibits an improved RT at higher temperature (125 °C).

Analytical Current Transport Modeling of Graphene Nanoribbon Tunnel Field-Effect Transistors for Digital Circuit Design

Abstract: A semi-classical and a semi-quantum current transport model for p-i-n n-type armchair graphene nanoribbon tunnel field effect transistor (TFET) are studied analytically. The results are compared with the numerical quantum transport simulation method using an atomistic Schrodinger–Poisson solver within the non-equilibrium Green function (NEGF) formalism. The channel length and width are 20 and 4.9 nm and a-GNR band gap is 0.289 eV. Current ratio ${\rm I_{ON}}/{\rm I_{OFF}}$ at 0.1 V supply voltage is calculated as follows: 122, 16.3 and 116 with a subthreshold slopes 26, 69 and 27.4 mV/decade from semi-classical, semi-quantum and NEGF simulation, respectively. Performance of a-GNR TFET is also studied analytically and numerically considering a-GNR width variation. Voltage transfer characteristics of a-GNR TFET inverter are computed for 0.1 V and 0.2 supply voltages using three current transport models which are in close agreement.

Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

Abstract: The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson's equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.

Impact of trap-assisted tunneling and channel quantization on InAs/Si hetero Tunnel FETs

Abstract: As a potential candidate for solid-state switches in low-power electronic circuits, the Tunnel Field Effect Transistor (TFET) has attracted the attention of device designers in the past few years. Although simulations have shown that ideal hetero TFETs can achieve sub-thermal sub-threshold swing (SS), the fabrication of a TFET with sufficient on-current and sub-thermal SS over a few decades of drain current remains to be done. Non-idealities in a TFET such as interface traps, band tails, or surface roughness exhibit stronger influence on TFET characteristics in the sub-threshold region. In Ref. [1] we observed that among all of these non-idealities the strongest effect is due to interface traps. On the other hand, simulations have shown that channel quantization severely degrades the on-current [2]. In this work, we analyse experimental transfer characteristics of InAs/Si nanowire TFETs (diameter « 100 nm) and find reasons for the degradation of SS and on-current. We give an estimate for the D it that still would allow a sub-thermal SS.

Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack

Abstract: The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2 V switching voltage) to realize next-generation state-of-the-art devices.

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

Abstract: In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

High frequency performance of dual metal gate vertical tunnel field effect transistor based on work function engineering

Abstract: A novel dual metal gate doping-less vertical tunnel field effect transistor (D-VTFET) on silicon body, using work function engineering is proposed. The proposed structure does not required impurity doping for formation of the drain and the source regions. In this concern, source and drain regions are formed by selecting appropriate work-function of metal electrode. The source and drain regions are not formed by conventional ways of ion implantation or diffusion. Hence, proposed structure is immune greatly to the process variation, issues of doping control and random dopant fluctuations which are serious problems in ultrathin silicon devices. For further improvement in ON state current and analogue/RF figures of merit dual work function of single gate material is considered. The electrical characteristics of the proposed device with the D-VTFET are simulated and compared.

Universal Charge-Conserving TFET SPICE Model Incorporating Gate Current and Noise

Abstract: An analytical compact model for tunnel field-effect transistor (TFET) circuit simulation is extended by adding a gate tunnel current model, a charge-based capacitor model, and a noise model. The equation set is broadly applicable across materials systems and TFET geometries and is readily fitted to rigorous physics-based device simulations and experimental results. To validate the gate current and charge models, technology computer-aided design (TCAD) simulations of a GaN/InN/GaN TFET are used. TCAD simulations show that the gate tunneling current depends on the gate-drain bias with a 100%/0% drain/source current partition. Terminal capacitances evaluated from the charge model agree well with simulations. The model is implemented in Verilog-A and the significance of gate current in the circuit design is illustrated in an amplifier design.

Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach

Abstract: In this paper, a first qualitative study on the performance characteristics of dual-work function gate junctionless TFET (DWG-JLTFET) on the basis of energy band profile modulation is investigated. A dual-work function gate technique is used in a JLTFET in order to create a downward band bending on the source side similar to PNPN structure. Compared with the single-work function gate junctionless TFET (SWG-JLTFET), the numerical simulation results demonstrated that the DWG-JLTFET simultaneously optimizes the ON-state current, the OFF-state leakage current, and the threshold voltage and also improves average subthreshold slope. It is illustrated that if appropriate work functions are selected for the gate materials on the source side and the drain side, the JLTFET exhibits a considerably improved performance. Furthermore, the optimization design of the tunnel gate length (L Tun) for the proposed DWG-JLTFET is studied. All the simulations are done in Silvaco TCAD for a channel length of 20 nm using the nonlocal band-to-band tunneling (BTBT) model.

Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

Abstract: In this paper, a gate-all-around junctionless tunnel field effect transistor (JLTFET) based on heterostructure of compound and group III–V semiconductors is introduced and simulated. In order to blend the high tunneling efficiency of narrow band gap material JLTFETs and the high electron mobility of III–V JLTFETs, a type I heterostructure junctionless TFET adopting Ge–Al x Ga1−x As–Ge system has been optimized by numerical simulation in terms of aluminum (Al) composition. To improve device performance, we considered a nanowire structure, and it was illustrated that high-performance logic technology can be achieved by the proposed device. The optimal Al composition founded to be around 20 % (x = 0.2). The numerical simulation results demonstrate that the proposed device has low leakage current I OFF of ~1.9 × 10−17, I ON of 4 µA/µm, I ON/I OFF current ratio of 1.7 × 1011 and subthreshold swing SS of 12.6 mV/decade at the 40 nm gate length and temperature of 300 K.

Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications

Abstract: Tunnel field effect transistor (TFET) is being considered as an alternative to the conventional MOSFETs for low power system on chip applications. In this Letter, gate-drain underlap (UL) feature of double gate TFET for analogue/RF characteristic is discussed. Here, it is found that parasitic resistance induced by gate drain UL is not significant as compared with DG tunnel field effect transistor (DG-FET). Thus, the behaviour of RF figure of merit is different from DG-FET.

Physics-based simulation study of high-performance gallium arsenide phosphide–indium gallium arsenide tunnel field-effect transistor

Abstract: For the first time, this work presents a novel combination of gallium arsenide phosphide (GaAsP) and indium gallium arsenide (InGaAs) as drain/channel and source materials, respectively, of tunnel field-effect transistor (TFET) for high-performance ultra-low-power applications. With this combination, the ON-state current of the proposed device is improved ten times as compared with GaAs–Ge TFET; however, the ambipolar current remains equal to the OFF-state current. It also exhibits a very low threshold voltage (half in amount) as compared with GaAs–Ge TFET. Apart from these, GaAsP–InGaAs TFET shows huge reduction in the subthreshold slope for better switching operation.

Dual workfunction hetero gate dielectric tunnel field-effect transistor performance analysis

Abstract: This paper features a study of DC and analog/RF response of dual work function hetero gate dielectric source pocket tunnel field-effect transistor (DW HGD SP TFET). For this, source pocket is used to enhance the tunneling of charge carrier results in increment in ON-state current. Further, the hetero gate dielectric is used to reduce the gate to drain capacitance which is a crucial parameter for RF performance determination. At the same time, work function engineering is useful to enhance the device performance in terms of ON-state current which influences the analog/RF performance but it is also increases the gate to drain capacitance which limits the RF parameters. Thus, combination of hetero gate dielectric and work function engineering provides an integrated effect on the device RF performance. In this regards, RF parameters such as transconductance, cutoff frequency, gain bandwidth product and transit time are calculated to analysis the device suitability in wireless communication.

TCAD simulation of germanium source dopingless tunnel FET

Abstract: In this paper, we investigated two dimensional simulation study of a germanium source doping-less tunnel field effect transistor (TFET). Use of low band gap material such as germanium is an effective way to increase tunneling. By using germanium at only source side off current increases less in compare to whole germanium device. By presenting the comparative study of conventional doping-less TFET and germanium source doping-less TFET we demonstrated that germanium source doping-less TFET have much better on current. Dopingless devices uses low thermal budget for fabrication so germanium source dopingless TFET's are suitable candidate for low power low cost devices.

Performance enhancement of asymmetrical underlap 3D-cylindrical GAA-TFET with low spacer width

Abstract: A comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high I ON (6.9 × 10−4 A/µm), low I OFF (2.5 × 10−17 A/µm), and an enhanced I ON/I OFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET.

Fabrication and electrical characterization of homo- and hetero-structure Si/SiGe nanowire Tunnel Field Effect Transistor grown by vapor–liquid–solid mechanism

Abstract: We demonstrate the fabrication and electrical characterization of Ω -gate Tunnel Field Effect Transistors (TFET) based on p-Si/i-Si/n+Si0.7Ge0.3 heterostructure nanowires grown by Chemical Vapor Deposition (CVD) using the vapor–liquid–solid (VLS) mechanism. The electrical performances of the p-Si/i-Si/n+Si0.7Ge0.3 heterostructure TFET device are presented and compared to Si and Si0.7Ge0.3 homostructure nanowire TFETs. We observe an improvement of the electrical performances of TFET with p-Si/i-Si/n+Si0.7Ge0.3 heterostructure nanowire (HT NW). The optimized devices present an Ion current of about 245 nA at VDS = −0.5 V and VGS = −3 V with a subthreshold swing around 135 mV/dec. Finally, we show that the electrical results are in good agreement with numerical simulation using Kane’s Band-to-Band Tunneling model.

Highly scaled tunnel FET with tight pitch and method to fabricate same

Abstract: A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes.

Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design

Abstract: Performance of graphene nanoribbon (GNR) tunnel field effect transistor (TFET) has been modeled in Verilog-Analog (Verilog-A) using previously reported physics based compact analytical current transport model. Performance obtained using both analytical model and Verilog-A simulations are compared providing excellent match. Using n-type and p-type GNR TFETs, inverter circuit is designed and simulated in Mentor Graphics® Tanner EDA S-Edit and T-Spice utilizing the developed Verilog-A codes. With suitable choice of supply voltage, our Verilog-A simulated GNR TFET inverter provides low propagation delay, low power dissipation and retains strong signal integrity.