H
Hafez Walid M
Researcher at Intel
Publications - 103
Citations - 1431
Hafez Walid M is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Gate dielectric. The author has an hindex of 17, co-authored 103 publications receiving 1367 citations.
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications
Chia-Hong Jan,M. Agostinelli,H. Deshpande,Mohammed A El-Tanani,Hafez Walid M,U. Jalan,L. Janbay,M. Kang,Hasnain Lakdawala,J. Lin,Y-L Lu,S. Mudanai,Joodong Park,Abdur Rahman,Jad B. Rizk,W.-K. Shin,Krishnamurthy Soumyanath,H. Tashiro,Curtis Tsai,P. Vandervoorn,J.-Y. Yeh,P. Bai +21 more
TL;DR: In this article, the authors examined the impact of silicon technology scaling trends and associated technological innovations on RF CMOS device characteristics, and the application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance.
Proceedings Article
A 1.1 GHz 12 μA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
Yih Wang,Hong Jo Ahn,Uddalak Bhattacharya,Zhanping Chen,T. Coan,Fatih Hamzaoglu,Hafez Walid M,Chia-Hong Jan,Pramod Kolar,Sarvesh H. Kulkarni,J. Lin,Yong-Gee Ng,Ian R. Post,Liqiong Wei,Ying Zhang,Kevin Zhang,Mark T. Bohr +16 more
TL;DR: A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications that improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage.
Proceedings ArticleDOI
A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products
C.-H. Jan,F. Al-Amoody,Chang Hsu-Yu,Tsung-Yuan Chang,Y.-W. Chen,N. L. Dias,Hafez Walid M,D. Ingerly,M. Jang,Eric Karl,S. K.-Y. Shi,K. Komeyli,H. Kilambi,A. Kumar,K. Byon,Chen-Guan Lee,J. Lee,T. Leo,Pei-Chi Liu,Nidhi Nidhi,Olac-Vaw Roman W,C. Petersburg,K. Phoa,Chetan Prasad,C. Quincy,Ramaswamy Rahul,T. Rana,L. Rockford,Anand Subramaniam,Curtis Tsai,P. Vandervoorn,L. Yang,A. Zainuddin,P. Bai +33 more
TL;DR: A leading edge 14 nm SoC platform technology based upon the 2nd generation Tri-Gate transistor technology has been optimized for density, low power and wide dynamic range and a full suite of analog, mixed-signal and RF features are supported.