Journal ArticleDOI
A million spiking-neuron integrated circuit with a scalable communication network and interface
Paul A. Merolla,John V. Arthur,Rodrigo Alvarez-Icaza,Andrew S. Cassidy,Jun Sawada,Filipp Akopyan,Bryan L. Jackson,Nabil Imam,Chen Guo,Yutaka Nakamura,Bernard Brezzo,Ivan Vo,Steven K. Esser,Rathinakumar Appuswamy,Brian Taba,Arnon Amir,Myron D. Flickner,William P. Risk,Rajit Manohar,Dharmendra S. Modha +19 more
TLDR
Inspired by the brain’s structure, an efficient, scalable, and flexible non–von Neumann architecture is developed that leverages contemporary silicon technology and is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification.Abstract:
Inspired by the brain’s structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the architecture to a cortexlike sheet of arbitrary size. The architecture is well suited to many applications that use complex neural networks in real time, for example, multiobject detection and classification. With 400-pixel-by-240-pixel video input at 30 frames per second, the chip consumes 63 milliwatts.read more
Citations
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Journal ArticleDOI
Demonstration of Unsupervised Learning With Spike-Timing-Dependent Plasticity Using a TFT-Type NOR Flash Memory Array
Chul-Heung Kim,Soochang Lee,Sung Yun Woo,Won-Mook Kang,Suhwan Lim,Jong-Ho Bae,Jaeha Kim,Jong-Ho Lee +7 more
TL;DR: An approach is suggested to implement a hardware neural network using the conventional CMOS technology for STDP unsupervised learning as a visual pattern recognition system.
Posted Content
Spike-FlowNet: Event-based Optical Flow Estimation with Energy-Efficient Hybrid Neural Networks
TL;DR: Spike-FlowNet is presented, a deep hybrid neural network architecture integrating SNNs and ANNs for efficiently estimating optical flow from sparse event camera outputs without sacrificing the performance.
Journal ArticleDOI
Field-Programmable Crossbar Array (FPCA) for Reconfigurable Computing
TL;DR: In this paper, the authors proposed a memory-centric, reconfigurable, general purpose computing platform that is capable of handling the explosive amount of data in a fast and energy-efficient manner.
Proceedings ArticleDOI
A self-driving robot using deep convolutional neural networks on neuromorphic hardware
TL;DR: In this paper, a closed-loop battery-powered communication system between an IBM Neurosynaptic System (IBM TrueNorth chip) and an autonomous Android-Based Robotics platform is presented.
Posted Content
A Tandem Learning Rule for Effective Training and Rapid Inference of Deep Spiking Neural Networks.
TL;DR: The proposed tandem learning rule offers a novel solution to training efficient, low latency, and high-accuracy deep SNNs with low computing resources and demonstrates competitive pattern recognition and regression capabilities on both the conventional frame- and event-based vision datasets.
References
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Receptive fields, binocular interaction and functional architecture in the cat's visual cortex
David H. Hubel,Torsten N. Wiesel +1 more
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Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs
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Object vision and spatial vision: two cortical pathways
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Modality and topographic properties of single neurons of cat's somatic sensory cortex.
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Neuronal circuits of the neocortex
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