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Journal ArticleDOI

A Practical Implementation of Silicon Microchannel Coolers for High Power Chips

TLDR
In this paper, the authors describe a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors, which is able to cool chips with average power densities of 400W/cm2 or more.
Abstract
This paper describes a practical implementation of a single-phase Si microchannel cooler designed for cooling very high power chips such as microprocessors. Through the use of multiple heat exchanger zones and optimized cooler fin designs, a unit thermal resistance 10.5 C-mm2 /W from the cooler surface to the inlet water was demonstrated with a fluid pressure drop of <35kPa. Further, cooling of a thermal test chip with a microchannel cooler bonded to it packaged in a single chip module was also demonstrated for a chip power density greater than 300W/cm2. Coolers of this design should be able to cool chips with average power densities of 400W/cm2 or more

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Citations
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Journal ArticleDOI

3D Integrated Water Cooling of a Composite Multilayer Stack of Chips

TL;DR: In this article, a multiscale conjugate heat transfer model is developed for integrated water cooling of chip layers and validated with experimental measurements on an especially designed thermal test vehicle that simulates a four tier chip stack with a footprint of 1 cm 2.
Proceedings ArticleDOI

Thermal modeling for 3D-ICs with integrated microchannel cooling

TL;DR: A fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs, which achieves more than 400× speed up and only 2.0% error in comparison with a commercial numerical simulation tool is presented.
Journal ArticleDOI

Optimizing CMOS technology for maximum performance

TL;DR: In this article, a processor-level technology-optimization program is presented to study the characteristics of optimal CMOS technology across many generations of CMOS, including high-k gate insulators, metal gates, high-mobility semiconductors, improved heat removal, and the use of multiple layers of circuitry.
Journal ArticleDOI

Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules

TL;DR: In this paper, an integrated liquid cooling system for 3D stacked modules with high dissipation level is proposed, and the fluidic interconnects in this system are elaborated and the sealing technique for different fluid interfaces is discussed.
References
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Journal ArticleDOI

High-performance heat sinking for VLSI

TL;DR: In this paper, a water-cooled integral heat sink for silicon integrated circuits has been designed and tested at a power density of 790 W/cm2, with a maximum substrate temperature rise of 71°C above the input water temperature.
Journal ArticleDOI

Challenges, developments and applications of silicon deep reactive ion etching

TL;DR: In this article, an optimized hardware for balanced RF drive at high power levels (3 kW) of the inductive plasma source in combination with spatial ion discrimination and collimation yields etch-rates in excess of 10 µm/min with excellent uniformity of profile and rate distribution.
Proceedings ArticleDOI

Micro-channel heat exchanger optimization

G.M. Harpole, +1 more
TL;DR: In this article, a complete two-dimensional flow/thermal model of the micro-channel cooler was developed, and the design parameters were optimized for the case of a 1 kW/cm/sup 2/ heat flux with the top surface at 25 degrees C.
Proceedings ArticleDOI

Single-Phase Heat Transfer Enhancement Techniques in Microchannel and Minichannel Flows

TL;DR: In this article, the applicability of single-phase heat transfer enhancement techniques for microchannels and minichannels is evaluated, where the major techniques include flow transition, boundary layer, entrance region, vibration, electric fields, swirl flow, secondary flow and mixers.
Journal ArticleDOI

Cooling characteristics of diamond-shaped interrupted cooling fin for high-power LSI devices

T. Kishimoto, +1 more
- 23 Apr 1987 - 
TL;DR: In this paper, a diamond-shaped interrupted microgrooved cooling fin was proposed to decrease the junction temperature variation across the chip, and the analytical results indicated that the reduction in junction temperature was less than 25% compared with a conventional paralles-plate-shaped cooling fin.
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