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Journal ArticleDOI

Bubble evolution mechanism and defect repair during the fabrication of high-quality germanium on insulator substrate

TLDR
In this article, the authors investigated the effect of the annealing temperature and the time on the bubble evolution on the hydrogen ion (H+)-implanted germanium (Ge) substrate.
Abstract
We investigate the effect of the annealing temperature and annealing time on the bubble evolution on the hydrogen ion (H+)-implanted germanium (Ge) substrate. It is found that the H2 aggregates gradually with the increase of the annealing time, and the aggregation rate of the H2 increases with the increase of the annealing temperature. Low-temperature Ge/Si wafer bonding (a-Ge interlayer) and Smart-Cut™ technique are applied to fabricate high-quality Ge-on-insulator (GOI). It is proved that thick Ge film is more difficult to be exfoliated from the Ge substrate. As long as the pressure in the bubbles is high enough, although the bubbles do not burst on the Ge surface, the lateral diffusion of H2 may occur to trigger the exfoliation of the Ge film. The contact of the wafers leads to the lateral merging of the small bubbles, resulting in the increase of the bubble size at the edge of the big void. It is believed that high bonding strength between Ge and SiO2 is essential to resist the high pressure in the bubble for the successful exfoliation of the Ge film. The point defects in the Ge film can be totally eliminated either by high-temperature annealing or by nanosecond pulse laser annealing, resulting in the improvement of the Ge film quality.

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Tensile-Strained Germanium-on-Insulator Substrate Fabrication for Silicon-Compatible Optoelectronics

TL;DR: In this article, a tensile-strained germanium-on-insulator (GOI) substrate is fabricated using heteroepitaxy and layer transfer techniques to obtain a high-quality wafer-scale platform suitable for silicon-compatible optoelectronic device fabrication.
Journal ArticleDOI

Electronic properties and defect levels induced by <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline" id="d1e1065" altimg="si112.svg"><mml:mrow><mml:mi>n</mml:mi><mml:mo>/</mml:mo><mml:mi>p</mml:mi></mml:mrow></mml:math>-type defect-complexes in Ge

TL;DR: In this article , the authors presented the results of the hybrid density functional theory calculations of substitutional and interstitial defect-complexes (B Ge N i , N Ge B i , Al Ge P i , P Ge Al i , Ga Ge As i , As Ge Ga i , In Ge Sb i , and Sb Ge In i ) in Ge.
References
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Journal ArticleDOI

Short-channel effect in fully depleted SOI MOSFETs

TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Journal ArticleDOI

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

TL;DR: In this paper, deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si/sub 0.8/Ge/sub sub 0.2/ heterostructures to yield well matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices.
Journal ArticleDOI

Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

TL;DR: In this paper, a circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances and reverse current of the freewheeling diode into consideration is given to evaluate the switching characteristics.
Proceedings ArticleDOI

Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

TL;DR: In this article, a fabrication method that attains the "ideal" double-gate MOSFET device structure is reported, where the top and bottom gates are inherently self-aligned to the source/drain.
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