Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
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Book ChapterDOI
Scaling and Its Implications for the Integration and Design of Thin Film and Processes
TL;DR: In this paper, the authors discuss the consequences of diminishing dimensions, both horizontal and vertical, with possible future trends and challenges, and discuss the central theme that underlies this handbook: scaling.
Posted ContentDOI
Statistical Modelling of ft to Process Parameters in 30 nm Gate Length Finfets
B. Lakshmi,R. Srinivasan +1 more
TL;DR: In this paper, the effect of process variations on unity gain frequency (ft) in 30 nm gate length FinFET by performing extensive TCAD simulations was investigated, and it was found that ft is more sensitive to gate length, underlap, gateoxide thickness, channel and Source/Drain doping and less sensitive to source/drain width and length.
Book ChapterDOI
Nanoarchitectonics: Advances in Nanoelectronics
Kostantin Likharev,Kang L. Wang,Mihri Ozkan,Roman Ostroumov,Youssry Y. Botros,Kosmas Galatsis +5 more
Journal ArticleDOI
Design and Investigation of SiGe Heterojunction Based Charge Plasma Vertical TFET for Biosensing Application
TL;DR: In this paper, the authors explored the vertical tunnel FET with the incorporated layer of SiGe within the channel/source junction using TCAD and found the Subthreshold swing (SS) found to be 29.07mV/decade, high on/off current ratio of 109 in 50nm channel.
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