Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
Citations
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Journal ArticleDOI
100-nm n-/p-channel I-MOS using a novel self-aligned structure
TL;DR: In this article, a 100-nm n-/p-channel I-MOS with self-alignment and reduced number of photolithography masks has been fabricated, which leads to low fabrication cost, accelerated scaling down, and enhanced performance.
Proceedings ArticleDOI
Exploring “temperature-aware” design in low-power MPSoCs
TL;DR: This paper investigates the need for temperature-aware design in a low-power systems-on-a-chip and provides guidlines to delimit the conditions for which temperature aware design is needed.
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Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
TL;DR: The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits.
Journal ArticleDOI
Double-Gate finFETs as a CMOS Technology Downscaling Option: An RF Perspective
TL;DR: In this paper, the effect of gate-length downscaling on the RF performance of double-gate fin field effect transistors (finFETs) has been analyzed based on careful physical description.
Journal ArticleDOI
Two gates are better than one [double-gate MOSFET process]
Paul M. Solomon,Kathryn W. Guarini,Y. Zhang,K.K. Chan,E.C. Jones,Guy M. Cohen,A. Krasnoperova,M. Ronay,O. Dokumaci,H.J. Hovel,J.J. Bucchignano,C. Cabral,Christian Lavoie,V. Ku,Diane C. Boyd,K. Petrarca,J.H. Yoon,Inna V. Babich,J. Treichler,P. Kozlowski,J. Newbury,Christopher P. D'Emic,Raymond M. Sicina,J. Benedict,Hon-Sum Philip Wong +24 more
TL;DR: In this article, a planar self-aligned double-gate MOSFET was implemented, where a unique sidewall source/drain structure (S/D) permits selfaligned patterning of the back-gate layer after the S/D structure is in place.
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