Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
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Memristor Synapses for Neuromorphic Computing
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Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes
TL;DR: In this article, a dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects in DG MOSFETs.
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3-D Full-Band Monte Carlo Simulation of Hot-Electron Energy Distributions in Gate-All-Around Si Nanowire MOSFETs
Mahmud Reaz,Andrew M. Tonigan,Kan Li,M. Brandon Smith,M. W. Rony,Mariia Gorchichko,Andrew O'Hara,Dimitri Linten,Jerome Mitard,Jingtian Fang,En Xia Zhang,Michael L. Alles,Robert A. Weller,Daniel M. Fleetwood,Robert A. Reed,Massimo V. Fischetti,Sokrates T. Pantelides,Stephanie L. Weeden-Wright,Ronald D. Schrimpf +18 more
TL;DR: In this paper, the energy distributions of electrons in gate-all-around (GAA) Si MOSFETs are analyzed using full-band 3-D Monte Carlo (MC) simulations.
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A quasi-ballistic drain current, charge and capacitance model with positional carrier scattering dependency valid for symmetric DG MOSFETs in nanoscale regime.
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A Review on Transistors in Nano Dimensions
TL;DR: In this paper, a review on characterization of transistors in nano dimension for improving ICs integration was presented, focusing on fabrication technology and characterization of nanowire transistor, FinFET transistor, and carbon nanotube transistor and its applications.
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