Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
Citations
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A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching
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How Many Gates do we Need in a Transistor
TL;DR: The migration from single-gate to multiple- gate SOI transistors is inexorable but still includes a number of hesitations and dilemmas, so the main motivations, technological achievements, physics-related implications and future challenges are reviewed.
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New Analytical Model for Nanoscale Tri-Gate SOI MOSFETs Including Quantum Effects
TL;DR: In this article, an analytical model for tri-gate MOSFETs considering quantum effects is presented, which is based on the analytical solution of Schrodinger-Poisson's equation using variational approach.
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Comparative Study of Uniform Versus Supersteep Retrograde MOSFET Channel Doping and Implications for 6-T SRAM Yield
Nattapol Damrongplasit,Nuo Xu,Hideki Takeuchi,Robert John Stephenson,Nyles W. Cody,A. Yiptong,Xiangyang Huang,Marek Hytha,Robert J. Mears,Tiehui Liu +9 more
TL;DR: In this article, the benefit of supersteep retrograde (SSR) channel doping for suppressing short-channel effects in planar bulk MOSFET performance was studied via technology computer-aided design simulation of devices with gate length Lg = 28 nm.
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Analog to digital conversion: technical aspects
Patrick Loumeau,Jean-François Naviner,Herve Petit,Lirida Alves de Barros Naviner,Patricia Desgreys +4 more
TL;DR: The present possibilities in terms of receiver architectures are described and the gap between these limits and the ideal solution proposed is evaluated and superconductor technology applied to Adc may be a solution.
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