Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
Citations
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References
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Proceedings ArticleDOI
A folded-channel MOSFET for deep-sub-tenth micron era
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,E. Anderson,Hideki Takeuchi,K. Asano,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +8 more
TL;DR: In this paper, a quasi-planar fold-channel transistor structure was proposed for the vertical double-gate SOI MOSFETs, which improved the short channel effect immunities.
Proceedings ArticleDOI
Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?
TL;DR: In this paper, Monte Carlo simulation is used to explore the characteristics of an n-channel MOSFET at the presently perceived limits of scaling, including a transconductance as high as 2300 mS/mm and an estimated ring-oscillator delay of 1.1 ps.
Journal ArticleDOI
Subbreakdown drain leakage current in MOSFET
TL;DR: In this article, a band-to-band tunneling in Si in the drain/gate overlap region was proposed to limit the leakage current to 0.1 pA/µm.
Journal ArticleDOI
Trading speed for low power by choice of supply and threshold voltages
Dake Liu,Christer Svensson +1 more
TL;DR: In this article, the tradeoff between speed and power consumption for low power consumption in CMOS VLSI by using the supply voltage and the threshold voltage as variables was investigated.