Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
Citations
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Journal ArticleDOI
A new scaling theory for fully-depleted SOI double-gate MOSFET’s: including effective conducting path effect (ECPE)
TL;DR: In this article, a new scaling theory for fully-depleted double-gate (DG) SOI MOSFETs is established, which gives a guidance for the device design so that maintaining a precise subthreshold factor for given device parameters.
Journal ArticleDOI
Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET
TL;DR: In this article, a physically-based model for the threshold voltage and the subthreshold swing of GAA MOSFETs at low drain-source voltage based on an analytical solution of the two-dimensional (2-D) Poisson equation (in cylindrical coordinates) with the mobile charge term included.
Journal ArticleDOI
Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET
TL;DR: In this article, a self-consistent quantum mechanical simulator based on the contact block reduction (CBR) method was used to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices.
Journal ArticleDOI
A Carrier-Based Approach for Compact Modeling of the Long-Channel Undoped Symmetric Double-Gate MOSFETs
TL;DR: In this paper, a carrier-based approach is presented to develop a compact model for long-channel undoped symmetric double-gate MOSFETs. But the model is not suitable for the case of single-input single-output (SISO) MOSFs.
Journal ArticleDOI
Effective Low Leakage 6T and 8T FinFET SRAMs: Using Cells With Reverse-Biased FinFETs, Near-Threshold Operation, and Power Gating
TL;DR: The design techniques recommended by this brief can enable longer battery life for small sensor systems and thus greater reliability for Internet-of-Things (IoT) devices.
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