Journal ArticleDOI
Device scaling limits of Si MOSFETs and their application dependencies
David J. Frank,R.H. Dennard,E. J. Nowak,Paul M. Solomon,Yuan Taur,Hon-Sum Philip Wong +5 more
- Vol. 89, Iss: 3, pp 259-288
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TLDR
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.Abstract:
This paper presents the current state of understanding of the factors that limit the continued scaling of Si complementary metal-oxide-semiconductor (CMOS) technology and provides an analysis of the ways in which application-related considerations enter into the determination of these limits. The physical origins of these limits are primarily in the tunneling currents, which leak through the various barriers in a MOS field-effect transistor (MOSFET) when it becomes very small, and in the thermally generated subthreshold currents. The dependence of these leakages on MOSFET geometry and structure is discussed along with design criteria for minimizing short-channel effects and other issues related to scaling. Scaling limits due to these leakage currents arise from application constraints related to power consumption and circuit functionality. We describe how these constraints work out for some of the most important application classes: dynamic random access memory (DRAM), static random access memory (SRAM), low-power portable devices, and moderate and high-performance CMOS logic. As a summary, we provide a table of our estimates of the scaling limits for various applications and device types. The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.read more
Citations
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Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
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Electron and ambipolar transport in organic field-effect transistors.
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Nanoelectronics from the bottom up
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TL;DR: This review presents a brief summary of bottom-up and hybrid bottom- up/top-down strategies for nanoelectronics with an emphasis on memories based on the crossbar motif, including experimental demonstrations of key concepts such lithography-independent, chemically coded stochastic demultipluxers.
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FinFETs and Other Multi-Gate Transistors
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A single-atom transistor
Martin Fuechsle,Jill A. Miwa,Suddhasatta Mahapatra,Hoon Ryu,Sunhee Lee,Oliver Warschkow,Lloyd C. L. Hollenberg,Gerhard Klimeck,Michelle Y. Simmons +8 more
TL;DR: This work presents atomic-scale images and electronic characteristics of these atomically precise devices and the impact of strong vertical and lateral confinement on electron transport and discusses the opportunities ahead for atomic- scale quantum computing architectures.
References
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Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Scaling the Si MOSFET: from bulk to SOI to bulk
R.-H. Yan,Abbas Ourmazd,K.F. Lee +2 more
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Journal ArticleDOI
CMOS scaling into the nanometer regime
Yuan Taur,Douglas A. Buchanan,Wei Chen,David J. Frank,Khalid EzzEldin Ismail,Shih-Hsien Lo,George Anthony Sai-Halasz,R. Viswanathan,Hsing-Jen Wann,Shalom J. Wind,Hon-Sum Philip Wong +10 more
TL;DR: In this article, the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations are discussed, including power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays.
Journal ArticleDOI
Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's
TL;DR: In this article, an accurate determination of the physical oxide thickness is achieved by fitting experimentally measured capacitanceversus-voltage curves to quantum-mechanically simulated capacitance-versusvoltage results.