Proceedings ArticleDOI
Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay
K.F. Lee,Ran-Hong Yan,D.Y. Jeon,G.M. Chin,Y.O. Kim,Donald M. Tennant,B. Razavi,H.D. Lin,Y.G. Wey,E.H. Westerwick,M.D. Morris,R.W. Johnson,T.M. Liu,M. Tarsia,M. Cerullo,R.G. Swartz,Abbas Ourmazd +16 more
- pp 131-134
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TLDR
In this paper, the authors report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V.Abstract:
We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics. >read more
Citations
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Journal ArticleDOI
1.5 nm direct-tunneling gate oxide Si MOSFET's
Hiroki Sasaki,Mizuki Ono,Takashi Yoshitomi,Tatsuya Ohguro,S. Nakamura,Masanobu Saito,Hiroshi Iwai +6 more
TL;DR: In this paper, a 1.5 nm direct-tunneling gate oxide was used to achieve a transconductance of more than 1,000 mS/mm at a gate length of 0.09 /spl mu/m at room temperature.
Journal ArticleDOI
Scaling optoelectronic-VLSI circuits into the 21st century: a technology roadmap
TL;DR: An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of future CMOS technology.
Journal ArticleDOI
Impact of distributed gate resistance on the performance of MOS devices
TL;DR: In this article, the impact of gate resistance on cut-off frequency, maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths was analyzed.
Journal ArticleDOI
Performance trends in high-end processors
TL;DR: In this article, a first order cycle time model performance trends and limits for both bipolar and CMOS processors are projected based on a first-order cycle-time model, and the performance limits of bipolar and room temperature CMOS uniprocessors are shown.
Journal ArticleDOI
Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS
TL;DR: This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology.
References
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Journal ArticleDOI
Scaling the Si MOSFET: from bulk to SOI to bulk
R.-H. Yan,Abbas Ourmazd,K.F. Lee +2 more
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Journal ArticleDOI
Deep-submicrometer MOS device fabrication using a photoresist-ashing technique
TL;DR: In this paper, a photoresist-ashing process was developed which, when used in conjunction with conventional g-line optical lithography, permits the controlled definition of deep-submicrometer features.
Journal ArticleDOI
Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates
TL;DR: In this article, four types of frequency dividers were fabricated on SIMOX/SOI (separation by implanted oxygen/silicon on insulator) substrates, and a novel circuit among these four circuits showed the highest operation frequency of 1.2 GHz under 1-V supply voltage, with gate lengths of 0.15 and 0.1 mu m.
Proceedings ArticleDOI
High performance 0.1- mu m room temperature Si MOSFETs
Ran-Hong Yan,K.F. Lee,D.Y. Jeon,Y.O. Kim,B.G. Park,M.R. Pinto,Conor S. Rafferty,D.M. Tennant,E.H. Westerwick,G.M. Chin,M.D. Morris,K. Early,P. Mulgrew,William M. Mansfield,R.K. Watts,A.M. Voshchenkov,Jeffrey Bokor,R.G. Swartz,Abbas Ourmazd +18 more
TL;DR: In this paper, the design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed.