Showing papers on "Anodic bonding published in 1997"

Wire bonding in microelectronics : materials, processes, reliability, and yield

Abstract: Technical Introduction to the Second Edition. Ultrasonic Bonding Systems and Technologies (Including Ultrasonic Wire Bonding Mechanism). Some Aspects of Bonding Wire Characteristics That can Affect Bonding, Reliability, or Testing. Wire Bond Testing. Gold-Aluminum Intermetallic Compounds and Other Metallic Interface Reactions Encountered in Wire Bonding. Bond Failures Resulting from Gold-Plating Impurities and Conditions. Cleaning to Improve Bondability and Reliability. Mechanical Problems in Wire Bonding. High-Yield and Fine-Pitch Wire Bonding. Wire Bonding to Multichip Modules and Other Soft Substrates. Glossary. Index.

Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding*1

Abstract: An alternative route to existing silicon on insulator (SOI) material technologies such as SIMOX (separation by implanted oxygen) and BESOI (bonded and etch-back SOI) is the new Smart-Cut process, which appears to be a good candidate to achieve ULSI criteria. The Smart-Cut process involves two technologies: wafer bonding and ion implantation associated with a temperature treatment which induces a in-depth splitting of the implanted wafer. The details of the Smart-Cut process, the physical phenomena involved in the different technological steps such as hydrogen implantation related mechanisms and wafer bonding are discussed. The characteristics of the final structure in terms of thickness homogeneity, crystalline defects, surface microroughness, and electrical characterization are presented. Other applications of this process are also highlighted.

Low-temperature intermediate Au-Si wafer bonding; eutectic or silicide bond

Abstract: The actual mechanism involved in Au-Si wafer bonding is controversial. Usually a titanium or chromium layer is deposited in between the (oxidized) silicon substrate and the gold layer to ensure adhesion. The resulting bond of two such wafers after annealing is generally considered to be eutectic, however, the bond temperature required is higher than would be expected from the Au-Si eutectic temperature. Moreover, silicide grains are formed at the bonding interface. In this paper it is proposed that the actual bonding is initiated by the dissolution of the oxide layer by silicidation of the titanium adhesion/barrier layer. The subsequent direct Au-Si contact enables the formation of the euteetic phase. The silicidation is required to obtain the eutectic alloy with 19 at.% Si despite the Ti diffusion barrier. The bonding temperature required is, therefore, set by the silicidation process rather than by the eutectic phase. Several experiments have been designed to support this theory. AI-Si eutectic bonding has been investigated, as it is not complicated by an adhesion metal and experiments demonstrate reliable bonding close to its eutectic temperature. Moreover, a Ti/Au/Si/Au stack has been fabricated to be used as a eutectic solder, giving bonding at a temperature not affected by silicidation. Keywords Eutectic bonding Gold Silicide bonding Silicon Wafer bonding

Low temperature bonding for microfabrication of chemical analysis devices

Abstract: A low temperature bonding process was developed for the fabrication of microchip devices for liquid and heterogeneous phase chemical analysis. Photolithographically etched microchannels on glass substrates were closed by bonding a glass cover plate using a spin-on sodium silicate layer as an adhesive. Good channel sealing was achieved by curing at 90°C for 1 h or room temperature overnight. The fluidic performance of the device was evaluated by monitoring the electroosmotic flow on the chip. The results compared well with those obtained from devices made by high temperature direct bonding of the substrate and cover plate. The dielectric and mechanical strength for bonds, created using the low and high temperature methods, were compared. A dielectric strength of 400 kV cm−1 was obtained for the sodium silicate bonding and 1100 kV cm−1 for the high temperature bonding. Mechanical strength measurements gave a surface energy value of ≈2.7 J m−2 for sodium silicate bonding, compared to 6.5 J m−2 for direct bonding. The mechanical strength of glass bonds obtained with sodium silicate at low temperature was comparable to that reported for the sodium silicate bonding of silicon wafers at >200°C or by conventional direct bonding of oxidized silicon at 1400°C. The low temperature bonding performance is adequate for microfabricated fluidic devices that employ electrokinetic transport phenomena. The reduced temperature of the bonding process will allow chemical surface modification prior to bonding.

Analysis of Bonding‐Related Gas Enclosure in Micromachined Cavities Sealed by Silicon Wafer Bonding

Abstract: We investigated the bonding-related gases trapped inside the cavities of micromachined silicon test structures that had been sealed by silicon direct bonding or anodic bonding under vacuum conditions. The gas content inside the cavities was analyzed by quadruple mass spectroscopy. The magnitude of the residual gas pressure inside the cavities for different cavity layouts and for various bonding processes was monitored. In cavities bonded by low-temperature silicon direct bonding the residual gases are reaction products originating from the mating silicon surfaces during annealing. Inside the cavities mainly H 2 , H 2 O, and N 2 are found. The total gas pressure is primarily determined by the H 2 component. Cavities sealed by anodic bonding mainly contain O 2 , which originates from mobile oxygen ions inside the bonding glass. The residual gas pressure inside anodically bonded cavities depends neither on the applied bonding voltage nor on the bonding area surrounding each cavity.

A fluxless bonding technology using indium-silver multilayer composites

Abstract: A fluxless bonding process has been developed using indium-silver multilayer composites deposited on silicon and GaAs wafers in one high vacuum cycle to inhibit the oxidation of the bonding media. The in situ formation of AgIn/sub 2/ intermetallic outer layer protects the inner media from oxidation when exposed to atmosphere. The bonding process is performed at 180/spl deg/C temperature in inert environment to prevent oxygen from getting into the specimens. High quality joints are produced as confirmed by a scanning acoustic microscope. The joints are very uniform with a thickness of 4 /spl mu/m. Scanning electron microscopy (SEM) evaluations reveal that the joint is composed of indium matrix with embedded intermetallic grains. Neither flux nor scrubbing motion is used in the bonding process. The process should be valuable in manufacturing applications where the use of flux cannot be tolerated.

The Role of Surface Chemistry in Bonding of Standard Silicon Wafers

Abstract: Hydrophilic silicon surfaces become hydrophobic without microroughening after 200°C low energy hydrogen plasma cleaning. The fully hydrogen‐terminated silicon surfaces do not bond to each other, not even by the application of external pressure. A subsequent 400 to 600°C, 4 min thermal treatment in ultrahigh vacuum converts the wafer surfaces to hydrophilic and bondable which can be attributed to desorption of hydrogen from the surfaces. Hydrophobic silicon surfaces prepared by a dip in HF (without subsequent water rinse) are terminated by H and a small amount of F, or by H and a small amount of OH (after subsequent water rinse). Hydrogen bonding of Si‒F⋯(HF)⋯H‒Si or Si‒OH⋯(HOH)⋯OH‒Si across the two mating surfaces appears to be responsible for room temperature spontaneous hydrophobic or hydrophilic wafer bonding, respectively.

Microchip Coulter particle counter

Abstract: This paper presents a micro device employing the Coulter principle for counting and sizing of living cells and particles in liquid suspension. The microchip Coulter particle counter (/spl mu/CPC) has been employed in a planar silicon structure covered with glass, which enables detailed observation during operation. By sheathing of a nonconductive liquid on either side of an electrolyte, it is possible to optimize the sensitivity to a specific cell-size. A method for measuring the relative flow-rates between liquid phases with different conductivity is presented. The method utilizes the laminar flow and short contact time of liquids in microchannels. As a result, the width of the liquids can be controlled without knowing the actual flow rates. The /spl mu/CPC has been fabricated by standard microfabrication techniques, including RIE, wet silicon etching, metalization and anodic bonding.

Wafer bonding and H-implantation mechanisms involved in the Smart-cut® technology

Abstract: Silicon-on-insulator (SOI) material, mainly known for high-temperature and radiation hard niche applications, is now increasingly used for low power and low voltage devices. The new Smart-Cut® SOI process, which appears as a good candidate to reach ULSI criteria, is described. Effects of physical phenomena, such as H-implantation, stiffer bonding quality and wafer cleaning, are presented. Formation mechanisms of the various bonding defects are discussed and related to particles trapped at the interface. The understanding of these mechanisms enabled SOI wafers to be obtained without any macroscopic defect. Thermal dependence of the interface quality revealed by a selective chemical etching is presented. The Smart-Cut® process leads to the formation of an SOI structure with a high top silicon thickness homogeneity and a surface microroughness comparable with that of the silicon substrate.

Forming a crystalline semiconductor film on a glass substrate

Abstract: A method of forming a crystalline semiconductor film on a glass substrate is described. The method relies on heating the glass substrate to a temperature at or above its strain point during a deposition or processing of the semiconductor film. Alternatively an intermediate film of a low strain point material is deposited on the glass substrate before depositing the semiconductor material. The process relaxes stresses at temperatures above the strain point. At temperatures below the strain point, the stresses can be controlled by slow cooling and by appropriate selection of the thermal expansion coefficient. Normal soda lime glasses having low strain points may be used for the glass substrate.

Room temperature silicon wafer bonding with ultra‐thin polymer films

Abstract: [16] U. Kreibig, P. Zacharias, Z . Phys. 1970,231, 128. [17] A. Creighton, D. G. Eadon, J. Chem. Soc., Faraduy Truns. 1991, 87, 3881. [I81 U. Kreibig, Z. Phys. B 1978,31,39. [19] C. Kittel, Introduction to Solid State Physics, Wiley, New York 1986. [ZO] C. F. Bohren, D. R. Huffman, Scattering and Absorption of Light by Small Particles, Wiley, New York 1983. [21] S. Torquato, J. Appl. Phys. 1985,58,3790. 1221 U. Kreibig, L. Genzel, Surf Sci. 1985,156,671, [23] M. C. Buncick, R. J. Warmack, T. L. Ferrell, J. Opt. SOC. A m . 1987, 4, 927. [24] Z.-Y. Huang, G. Mills, B. Hajek, J . Phys. Chem. 1993,97, 11 542. 1251 J. F. Hamilton, T. H. James, Theory of the Photographic Process, 4th ed., Macmillan, New York 1978. [26] R. W. Gurney, N. E Mott, Proc. R. SOC. London A 1938,164,151. [27] E. J. Hart, M. Anbar, The Hydrated Electron. Wiley-Interscience. New York 1970. [28] E-Y. Jou, G. R. Freeman. J. Phys. Chem. 1977,81, 909.

Direct wafer bonding of III-V compound semiconductors for free-material and free-orientation integration

Abstract: This paper describes the use of direct wafer bonding technique to implement the novel concept of "free-material and free-orientation integration" which we propose. The technique is applied for various wafer combinations of an InGaAsP material system, and the properties of the bonded structures are studied in terms of the crystalline and electrical characterization through transmission electron microscope, X-ray diffraction, and so on. This technique's advantage for use in the fabrication of lattice-mismatched structures is confirmed by the crystalline characterization, together with its second advantage of enabling bonded structures with an orientation mismatch, is investigated. The high crystalline quality of the bonded structures with both lattice and orientation mismatches is proved, and the electrical property of the bonded interface is examined for some of them. We show a practicability in a laser fabricated on a lattice- and orientation-mismatched structure by direct bonding. The results demonstrate the remarkable feasibility of using the direct wafer bonding technique to obtain integrated structures of material- and orientation-mismatched wafers with satisfactory quality.

Room temperature GaAsSi and InPSi wafer direct bonding by the surface activated bonding method

Abstract: Epitaxial growth and metalorganic chemical vapor deposition of GaAs and other III–IV compounds on silicon substrate have been investigated extensively. Such methods, however, generally result in a high density of threading dislocation because of the large lattice mismatch and a large residual thermal stress because of a large difference in thermal expansion coefficients between Si and III–IV compound semiconductors. In order to overcome those method, other conventional direct bonding techniques have been re-examined. But, high temperature annealing of these processes may cause many problems, such as doping of impurity, thermal stress introduction, defect generation and metal wiring corruption. Therefore, a new technology of wafer direct bonding has been developed. In the procedure of the bonding, which is referred to the surface activated bonding (SAB), the surfaces to be bonded are sputter-cleaned and activated by argon fast atom beam (FAB) bombardment and then brought into contact with each other in an ultrahigh vacuum. Using the SAB method, GaAsSi and InPSi wafer were successfully bonded at room temperature.

Conductive polymer film bonding technique

Abstract: The specification describes a thermocompression bonding process using anisotropic conductive film (ACF) bonding material in which the bonding pads are shaped to prevent depletion of conductive particles in the bonding region during compression. The process is useful in bump technology for interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The shaped structure can be made using photodefinable polymer strips around the bonding pads where the strips are thicker than the bonding pad. Alternative approaches to shaping one or both of the mating conductive surfaces are disclosed.

Control of size and heat affected zone for fine pitch wire bonding

Abstract: The amount of a terminal portion of bonding wire which is melted to form a free air ball for ball bonding and the temperature rise in the bonding wire adjacent the free air ball is limited by quenching of the wire and free air ball with a flow of a gas which also effectively removes heat applied to the wire. Since the amount of melting of the bonding wire can be closely regulated, reduction of size and improvement of uniformity of the free air ball can be obtained for ball bonding at pitches of less than ninety mils even when bonding wire of reduced diameter is employed. Quenching of the bonding wire adjacent to the free air ball also limits the temperature rise in the bonding wire and the extent of a heat affected zone having less tensile strength and stiffness to less than one micron and with reduced grain enlargement. Thus wire bonding is provided for electronic packaging of increased reliability, potential functionality, increased manufacturing yield and reduced process complexity.

Optical switch and method for assembling the same

Abstract: An optical switch includes a substrate having therein optical waveguides made of silicon and a silicon layer deposited on its top surface A space is formed in the crossing portion of the optical waveguides which is covered with a lid, preferably made of low alkali borosilicate glass, and which is bonded to the silicon layer by anodic bonding Preferably, a groove is formed in a surface of the optical waveguide substrate or a bonding surface of the lid The groove, after the lid has been bonded, makes a passage which communicates between the space and an outside The passage is a pouring slit for pouring an index-matching liquid and is connected to the space which acts as a driving slit in which the index-matching liquid moves In one embodiment, the width of the pouring slit is smaller than that of the driving slit The optical switch can be manufactured by providing an optical waveguide substrate and a lid substrate, one of which is formed with a groove in its surface on which the two substrates are bonded The optical waveguide substrate and the lid substrate are bonded together by anodic bonding to make a passage which communicates between the space formed in a crossing portion of the optical waveguides and an outside The regulation of the volume of the index-matching liquid is time-, temperature-, or pressure-based regulation

Design of a modular micropump based on anodic bonding

Abstract: A simple and reliable technology for the fabrication of micromachined micropumps is presented The assembling of different wafers to produce valves and cavities is usually the critical step regarding final yield Our technology uses exclusively the well known anodic bonding technique for this purpose The prospective performance of the devices has been evaluated by finite element methods and system level simulations

Fusion bonding of rough surfaces with polishing technique for silicon micromachining

Abstract: Surface roughness is one of the crucial factors in silicon fusion bonding. Due to the enhanced surface roughness, it is almost impossible to bond wafers after KOH etching. This also applies when wafers are heavily doped, have a thick LPCVD silicon nitride layer on top or have a LPCVD polysilicon layer of poor quality. It has been demonstrated that these wafers bond spontaneously after a very brief chemical mechanical polishing step. An adhesion parameter, that comprises of both the mechanical and chemical properties of the surface, is introduced when discussing the influence of surface roughness on the bondability. Fusion bonding, combined with a polishing technique, will broaden the applications of bonding techniques in silicon micromachining.

Novel microstructures and technologies applied in chemical analysis techniques

Abstract: Novel glass and silicon microstructures and their application in chemical analysis are presented. The micro technologies comprise (deep) dry etching, thin layer growth and anodic bonding. With this combination it is possible to create high resolution electrically isolating silicon dioxide structures with aspect ratio's similar to those possible in silicon. Main applications are chemical separation methods such as high performance liquid chromatography (HPLC) or electrophoresis (HPCE). Beside these channel structures, a capillary connector with very low dead and mixing volume has been designed and fabricated for use in (correlation) electrophoresis, and tested by means of precision of consecutive single injections.

Spontaneous direct bonding of thick silicon nitride

Abstract: Wafers with LPCVD silicon-rich nitride layers have been successfully direct bonded to silicon-rich nitride and boron-doped silicon surfaces. A chemical - mechanical polishing treatment was necessary to reduce the surface roughness of the nitride before bonding. The measured surface energies of the room-temperature bond were comparable to values found for Si - Si hydrophilic bonding. A mechanism similar to this bonding is suggested for silicon nitride bonding.

Method of fabricating direct-bonded semiconductor wafers

Abstract: A method of direct-bonding semiconductor wafers limits the time interval between a bonding step and a bonding anneal step or performs a baking step between the bonding and bonding anneal steps at a predetermined temperature for a predetermined time interval to prevent the formulation of voids on the edge regions of the wafers. The method for fabricating laminated semiconductor wafers includes a bonding step to fit together two polished semiconductor wafers by bonding jigs, and a succeeding bonding anneal step to laminate the wafers. In the method the bonding anneal step is preferably carried out within an hour following the bonding step; or a baking step at a predetermined temperature for a predetermined time interval is carried out between the bonding step and the bonding anneal step. Further, the method can prevent heavy metal impurities attached to the surface of the wafer from diffusing into the wafer by baking the wafer for over 5 minutes at above 100° C. in the period between the bonding step and the annealing step.

Gas tightness of cavities sealed by silicon wafer bonding

Abstract: The hermetic sealing of cavities formed by low temperature silicon direct bonding (SDB) and anodic bonding (AB) of plain and structured silicon surfaces is quantitatively investigated: Gas leakage rates along the bonding interface are determined for pressure sensor test structures by monitoring the pressure increase after a 700 h storage in a 6 bar hydrogen atmosphere. Corresponding leakage rates under atmospheric conditions as small as 10/sup -14/ (mbar 1)/s could be determined by this method. In the case of AB and of hydrophilic SDB with plain bonding surfaces, no measurable gas leakage is observed. For SDB however, only 6 nm deep grooves on one bonding surface do already cause a considerable gas leakage. For AB grooves with a depth of up to ca. 50 nm are still perfectly sealed. Here, the electrostatic pressure leads to a surface conformation through mainly elastic deformation of the bonding surfaces.

Ferroelectric-semiconductor heterostructures obtained by direct wafer bonding

Abstract: A novel fabrication process of ferroelectric-semiconductor heterostructures based on direct wafer bonding has been demonstrated. Polycrystalline Bi4Ti3O12 ferroelectric thin films were deposited on 3 in. silicon wafers using chemical solution deposition. The films were polished and then directly bonded to silicon wafers in a micro-cleanroom. After thermal annealing in air at 500 °C for 12 h, the bonding energy increases up to 1.5 J/m2. High resolution transmission electron microscopy shows the difference between the bonded and reacted interfaces. Obtaining a metal-ferroelectric-silicon (MFS) structure containing the ferroelectric-Si bonded interface was achieved by polishing down and etching the handling wafer. The Bi4Ti3O12 film kept its ferroelectric properties as shown by C–V measurement.

CMOS compatible wafer scale adhesive bonding for circuit transfer

Abstract: Reports on a transfer technique for CMOS circuits based on a newly developed bonding technique, namely wafer scale adhesive bonding using epoxies. The circuit transfer sequence consists of three steps: bonding a CMOS processed SIMOX wafer to a Pyrex glass wafer, thinning the SIMOX wafer down to the buried oxide and exposing the contact pads. A test chip was designed to evaluate the impact of circuit transfer on the device performance. Measurements have shown a slight increase in leakage current and a small change of threshold voltage due to stress induced by the circuit transfer.

Microsystems and wafer processes for volume-production of highly reliable fiber optic components for telecom- and datacom-application

Abstract: In development and fabrication of highly reliable active fiber optic components, first the application of great fields of microsystem techniques enabled the breakthrough in volume-production. Micro-mechanical methods allowed the big scale fabrication of microoptical silicon lenses with methods, machines and materials of the semiconductor technology on wafer. With the simultaneous application of micro-mechanical methods, such as anodic bonding processes of optical components and semiconductor-laser heated solder bonding techniques, it was possible to realize also hybrid integrated fiberoptic subcomponents on silicon wafer with the neccessary dimensions, tolerances and mechanical stability in the submicrometer region. We have realized a technology with micro-systems that enables on an (about 1 mm sq.) chip in a silicon wafer compound the hybrid integration of complete active fiberoptic modules with their different active semiconductor chips and the micro-optics for direct coupling in and out of the SM- and MM-fibers for different applications. With this technology of a compact design of the neccessary materials and components we could assemble components as laser- and detector-modules with the highest standard of microoptical stability and reliability. With this technique we can use the already in microelectronics well-established low cost production methods on wafer scale also for active fiber optic components. This means the complete fabrication, burn-in and testing procedures are practicable for example on a 5 inch silicon-wafer. So the main module-functions are separated from the cost intensive packaging efforts. It is rather possible to provide with a standard-submount base-component a fiber optic product family for different applications with adapted packages. This means that on the base of these module-subcomponents the volume production as well of low cost as also of high end components for fiber optics are possible. As all the essential opto-electrical and mechanical functions are combined in the highly stable subcomponent chip with well adapted materials, in minimal dimensions and symmetrical design, all the derived fiber optic components can provide the imperative reliability for these products. In some examples we show proposed exploitations of these technique for highly expedient realization of fiber optic transmission systems. One very important field for application of low cost components is the access network. Fiber to the home needs medium datarates (up to 155 Mbit/s) and medium length (up to 10 km). The techniques described here allows to find the optimum between performance and cost for these applications. Using the bi-directional transmission the effort for the bit transport can be reduced near to the level of copper lines. Therefore the German Telekom has installed a lot of subscriber lines using modules for bi-directional optical transmission.

Anodic bonding technique under low temperature and low voltage using evaporated glass

Abstract: A silicon-to-silicon anodic bonding process using a glass layer deposited by electron beam evaporation will be described. Wafers are bonded at a temperature as low as 135 °C with an applied voltage as small as 35 Vdc, enabling this technique to be applied to vacuum packaging of microelectronic devices. Experimental results reveal that an evaporated glass layer of more than 1 μm thick is suitable for anodic bonding. Finally, the role of sodium ions in anodic bonding was also studied by investigating the theoretical bonding mechanism and examining the results of secondary ion mass spectroscopy analysis.

Electromagnetically shielding bonding film

Abstract: Provided is bonding film in the form of web which has a high electromagnetic shielding effect for electromagnetic radiation from the front surface of a display device, and other favorable properties such as an infrared blocking property, a transparency, a invisibility and a favorable bonding property. The bonding film typically includes base film, a geometrically patterned electroconductive layer placed over the base film so as to achieve an aperture ratio of 80% of more, and a bonding layer for attaching the assembly to an object. The film may be applied to the surface of a transparent sheet member for the convenience of handling, and such an assembly has a symmetric structure so that the warping of the assembly may be minimized. The bonding film may be interposed between a pair transparent base sheets, or the bonding film may be applied over two sides a transparent base sheet. The assembly may further include an infrared blocking layer and an anti-glare layer.

Substrate bonding techniques for CMOS processed wafers

Abstract: Transferring a CMOS circuit to a foreign substrate can be accomplished by bonding a processed silicon wafer to the substrate and subsequently thinning the silicon wafer. This paper presents both anodic bonding and adhesive bonding and evaluates their potential for circuit transfer.