Showing papers on "Parasitic capacitance published in 2010"

Eliminating Ground Current in a Transformerless Photovoltaic Application

Abstract: For low-power grid-connected applications, a single-phase converter can be used. In photovoltaic (PV) applications, it is possible to remove the transformer in the inverter to reduce losses, costs, and size. Galvanic connection of the grid and the dc sources in transformerless systems can introduce additional ground currents due to the ground parasitic capacitance. These currents increase conducted and radiated electromagnetic emissions, harmonics injected in the utility grid, and losses. Amplitude and spectrum of the ground current depend on the converter topology, the switching strategy, and the resonant circuit formed by the ground capacitance, the converter, the ac filter, and the grid. In this paper, the ground current in a 1.5-kW PV installation is measured under different conditions and used to build a simulation model. The installation includes a string of 16 PV panel, a full-bridge inverter, and an LCL filter. This model allows the study of the influence of the harmonics injected by the inverter on the ground current.

Modulation Techniques to Eliminate Leakage Currents in Transformerless Three-Phase Photovoltaic Systems

Abstract: In some photovoltaic (PV) applications, it is possible to remove the transformer of a system in order to reduce losses, cost, and size. In transformerless systems, the PV module parasitic capacitance can introduce leakage currents in which the amplitude depends on the converter topology, on the pulsewidth modulation, and on the resonant circuit comprised by the system components. Based on the common-mode voltage model, modulation techniques are proposed to eliminate the leakage current in transformerless PV systems without requiring any modification on the converter and any additional hardware. The main drawback is that the proposed modulation technique for two-level inverters can only be used with 650-V dc link in the case of a 110-V (rms) grid phase voltage. Comparisons among the modulation techniques are discussed, and it is proven that the proposed modulation for two- and three-level inverters presents the best results. To validate the models used in the simulations, an experimental three-phase inverter is used.

A 6- $\mu$ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

Abstract: An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.

Tunneling Field-Effect Transistor: Capacitance Components and Modeling

Abstract: We report a numerical simulation study of gate capacitance components in a tunneling field-effect transistor (TFET), showing key differences in the partitioning of gate capacitance between the source and drain as compared with a MOSFET. A compact model for TFET capacitance components, including parasitic and inversion capacitances, was built and calibrated with computer-aided design data. This model should be useful for further investigation of performance of circuits containing TFETs. The dependence of gate-drain capacitance Cgd on drain design and gate length was further investigated for reduction of switching delay in TFETs.

A robust, low-cost and low-noise artificial skin for human-friendly robots

Abstract: As robots and humans move towards sharing the same environment, the need for safety in robotic systems is of growing importance. Towards this goal of human-friendly robotics, a robust, low-cost, low-noise capacitive force sensing array is presented with application as a whole body artificial skin covering. This highly scalable design provides excellent noise immunity, low-hysteresis, and has the potential to be made flexible and formable. Noise immunity is accomplished through the use of shielding and local sensor processing. A small and low-cost multivibrator circuit is replicated locally at each taxel, minimizing stray capacitance and noise coupling. Each circuit has a digital pulse train output, which allows robust signal transmission in noisy electrical environments. Wire count is minimized through serial or row-column addressing schemes, and the use of an open-drain output on each taxel allows hundreds of sensors to require only a single output wire. With a small set of interface wires, large arrays can be scanned hundreds of times per second and dynamic response remains flat over a broad frequency range. Sensor performance is evaluated on a bench-top version of a 4×4 taxel array in quasi-static and dynamic cases.

A high-performance top-gate graphene field-effect transistor based frequency doubler

Abstract: A high-performance top-gate graphene field-effect transistor (G-FET) is fabricated, and used for constructing a high efficient frequency doubler. Taking the advantages of the high gate efficiency and low parasitic capacitance of the top-gate device geometry, the gain of the graphene frequency doubler is increased about ten times compared to that of the back-gate G-FET based device. The frequency response of the frequency doubler is also pushed from 10 kHz for a back-gate device to 200 kHz, at which most of the output power is concentrated at the doubled fundamental frequency of 400 kHz.

180nm gate length amorphous InGaZnO thin film transistor for high density image sensor applications

Abstract: In this article, we propose a novel hybrid complementary metal oxide semiconductor (CMOS) image sensor architecture utilizing nanometer scale amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFT) combined with a conventional Si photo diode. This approach will overcome the loss of quantum efficiency and image quality due to the downscaling of the photodiode. The 180nm gate length a-IGZO TFT exhibits remarkable short channel device performance including a low 1/ƒ noise and a high output gain, despite fabrication temperatures as low as 200°C. The excellent device performance has been achieved by a double layer gate dielectric (Al 2 O 3 /SiO 2 ) and a trapezoidal active region formed by a tailored etching process. A self aligned top gate structure was employed for low parasitic capacitance. 3D process simulation tools were applied to optimize a four pixel CMOS image sensor structure. The results demonstrate how our stacked hybrid device approach contributes to new device strategies in image sensor architectures. We expect that this approach is applicable to numerous devices and systems in future micro- and nano-electronics.

Radio frequency electrical transduction of graphene mechanical resonators

Abstract: We report radio frequency (rf) electrical readout of graphene mechanical resonators. The mechanical motion is actuated and detected directly by using a vector network analyzer, employing a local gate to minimize parasitic capacitance. A resist-free doubly clamped sample with resonant frequency ∼34 MHz, quality factor ∼10 000 at 77 K, and signal-to-background ratio of over 20 dB is demonstrated. In addition to being over two orders of magnitude faster than the electrical rf mixing method, this technique paves the way for use of graphene in rf devices such as filters and oscillators.

A Resonant Gate-Drive Circuit Capable of High-Frequency and High-Efficiency Operation

Abstract: This paper deals with a new resonant gate-drive circuit for power MOSFETs. The proposed gate-drive circuit is characterized by a resonant inductor connected in series with the gate terminal of the driven MOSFET. The inductor and the input capacitance of the MOSFET form a series resonant circuit, which enables to charge or discharge the gate-to-source input capacitance of the MOSFET without any electric power consumption in theory. Experimental results are shown to verify the viability of the resonant gate-drive circuit. As a result, the proposed resonant gate-drive circuit reduces its power consumption by a factor of ten, compared with a conventional one. A 360-kHz and 1-kW MOSFET inverter driven by the proposed gate-drive circuits exhibits a high efficiency more than 99%, considering the losses in the two main MOSFETs and the two resonant gate-drive circuits.

Analysis and Applications of Parasitic Capacitance Cancellation Techniques for EMI Suppression

Abstract: This paper reviews and analyzes five parasitic capacitance cancellation methods. Critical parameters and constraints determining the cancellation frequency ranges are identified, and the effective frequency range for each cancellation method is derived based on these constraints. Due to these constraints, each method has specific advantages for certain applications. The cancellation techniques, which all make use of either mutual capacitance or mutual inductance, are applied to different applications based on their advantages, and the experiments are carried out to verify the analysis.

Methods and apparatus for capacitive sensing

Abstract: The present disclosure addresses methods and apparatus facilitating capacitive sensing using a conductive surface, and facilitating the sensing of proximity to the conductive surface The sensed proximity will often be that of a user, but can be another source of a reference voltage potential In some examples, the described systems are capable of sensing capacitance (including parasitic capacitance) in a circuit that includes the outer conductive surface, and where that outer conductive surface is at a floating electrical potential In some systems, the systems can be switched between two operating modes, a first mode in which the system will sense proximity to the conductive surface, and a second mode in which the system will use a capacitance measurement to sense contact with the conductive surface

Nanopores in solid-state membranes engineered for single molecule detection.

Abstract: A nanopore is an analytical tool with single molecule sensitivity. For detection, a nanopore relies on the electrical signal that develops when a molecule translocates through it. However, the detection sensitivity can be adversely affected by noise and the frequency response. Here, we report measurements of the frequency and noise performance of nanopores

Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback

Abstract: In this paper, a novel current-mode transimpedance amplifier (TIA) exploiting the common gate input stage with common source active feedback has been realized in CHRT 0.18 ?m -1.8 V RFCMOS technology. The proposed active feedback TIA input stage is able to achieve a low input impedance similar to that of the well-known regulated cascode (RGC) topology. The proposed TIA also employs series inductive peaking and capacitive degeneration techniques to enhance the bandwidth and the gain. The measured transimpedance gain is 54.6 dB? with a -3 dB bandwidth of about 7 GHz for a total input parasitic capacitance of 0.3 pF. The measured average input referred noise current spectral density is about 17.5 pA/?{Hz} up to 7 GHz. The measured group delay is within 65 ± 10 ps over the bandwidth of interest. The chip consumes 18.6 mW DC power from a single 1.8 V supply. The mathematical analysis of the proposed TIA is presented together with a detailed noise analysis based on the van der Ziel MOSFET noise model. The effect of the induced gate noise in a broadband TIA is included.

A CMOS Class-E Power Amplifier With Voltage Stress Relief and Enhanced Efficiency

Abstract: This paper proposes a class-E power amplifier (PA) with double-resonance circuit to reduce voltage stress on CMOS transistors. The voltage waveform applied to the CMOS transistor is shaped by harmonic control and the transistors are relieved from breakdowns. A negative capacitance is also implemented for efficiency enhancement, compensating for surplus capacitance from parasitic components on the drain node. Thus, nominal class-E operation is restored and high efficiency is achieved. We present a cascode differential class-E RF PA that is fabricated using a 0.13-? m CMOS technology that delivers 31.5-dBm output power with 54% drain efficiency and 51% power-added efficiency at 1.8 GHz.

Low-Noise Amplifier Design With Dual Reactive Feedback for Broadband Simultaneous Noise and Impedance Matching

Abstract: The simultaneous noise and impedance matching (SNIM) condition for a common-source amplifier is analyzed Transistor noise parameters are derived based on the more complete hybrid-? model, and the dominant factors jeopardizing SNIM are identified Strategies for narrowband and broadband SNIM (BSNIM) are derived accordingly A dual reactive feedback circuit along with an LC-ladder matching network is proposed to achieve the BSNIM It includes a capacitive and an inductive feedback, where the former utilizes the transistor parasitic gate-to-drain capacitance and the latter is formed by transformer coupling This circuit topology has been validated in 018- and 013- ?m CMOS technologies for a 3-11-GHz ultra-wideband (UWB) and a 24-54-GHz multistandard application, respectively The 3-11-GHz UWB low-noise amplifier is detailed as a design example

Projected capacitive touch-sensitive panel

Abstract: A touch-sensitive panel is described herein that includes a first sensor layer and a second sensor layer and at least one shield electrode integrated into the first sensor layer and/or the second sensor layer. The at least one shield electrode is operable to cancel parasitic capacitance between at least one sense electrode in the first sensor layer and at least one sense electrode in the second sensor layer. The integrated shield electrode(s) in the first sensor layer and/or the second sensor layer can be used in place of an additional shield layer to combat parasitic capacitance in the touch-sensitive panel, thereby reducing the cost and materials necessary to manufacture the touch-sensitive panel. A touch-screen display that includes such a touch-sensitive panel and a method of operating such a touch-sensitive panel are also described.

Systems for an electrostatic stylus within a capacitive touch sensor

Abstract: Systems are described for transmitting and receiving signals in an active stylus for a capacitive touch sensor, for which the systems have at least one circuit for receiving a current from an electrode and for transmitting a voltage onto the electrode. The systems include components for receiving the current in a receiving mode, a switch, and a switchmode power supply circuit having at least a transformer and a diode, for which the diode is coupled to the transformer. In a transmission mode, there is means for electrically isolating at least some of the components configured for receiving the current in the receiving mode from the voltage formed across the stray capacitance. In the receiving mode, there is a means for electrically isolating at least some of the components configured for receiving the current in the receiving mode from an inductance of the transformer in the switchmode power supply circuit.

Symmetric Adiabatic Logic Circuits against Differential Power Analysis

Abstract: We investigate the possibility of using adiabatic logic as a countermeasure against differential power analysis (DPA) style attacks to make use of its energy efficiency. Like other dual-rail logics, adiabatic logic exhibits a current dependence on input data, which makes the system vulnerable to DPA. To resolve this issue, we propose a symmetric adiabatic logic in which the discharge paths are symmetric for data-independent parasitic capacitance, and the charges are shared between the output nodes and between the internal nodes, respectively, to prevent the circuit from depending on the previous input data.

Parasitic Compensation Design Technique for a C-Band GaN HEMT Class-F Amplifier

Abstract: A class-F/inverse class-F load circuit design method that includes parasitic elements such as drain-source capacitance and bonding wire inductance has been developed. For the class-F load circuit design, a reactance function which has zeros at even harmonic frequencies and poles at odd harmonic frequencies is expanded to an -ladder circuit including parasitic elements through the use of the second Cauer canonical form. For the inverse class-F load circuit design, the zero points and the poles are exchanged. One stage of the -ladder circuit can be approximately replaced to a distributed circuit element for higher frequency operation. The proposed method allows parasitic compensation up to an arbitrary harmonic order by adding zeros and poles. Additionally, if distributed circuit elements are used, the method also compensates frequency dispersive characteristics of microstrip lines. According to the proposed method, a class-F amplifier using an AlGaN-GaN HEMT has been fabricated at 5.8 GHz. The fabricated class-F amplifier delivered high efficiency characteristics, with a maximum drain efficiency of 79.9%, a maximum power-added efficiency (PAE) of 71.4%, and an output power of up to 33.4 dBm at 5.86 GHz.

A Low Loss High Isolation DC-60 GHz SPDT Traveling-Wave Switch With a Body Bias Technique in 90 nm CMOS Process

Abstract: In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (P1 dB)> and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 × 0.87 mm2 with a core area of only 0.32 × 0.21 mm2.

Fabrication of n‐ and p‐Type Organic Thin Film Transistors with Minimized Gate Overlaps by Self‐Aligned Nanoimprinting

Abstract: [∗] U. Palfi nger , C. Auner , H. Gold , A. Haase , J. Kraxner , G. Jakopic , J. R. Krenn , B. Stadlober Institute of Nanostructured Materials and Photonics Joanneum Research GmbH Franz-Pichlerstrasse 30, A-8160 Weiz (Austria) Fax: 0043-316-876-2710 Telephone: 0043-316-876-2721 E-mail: barbara.stadlober@joanneum.at T. Haber , M. Sezen , W. Grogger Institute for Electron Microscopy Graz University of Technology Steyrergasse 17, A-8010 Graz (Austria) G. Domann Fraunhofer-Institut für Silicatforschung ISC Neunerplatz 2, D-97082 Würzburg (Germany)

Rotor-Position Estimation of Switched Reluctance Motors Based on Damped Voltage Resonance

Abstract: This paper proposes a method to obtain the rotor position of switched reluctance motors (SRMs) by means of voltage measurements. It is shown that the combination of a motor and a power-electronic converter defines a resonant circuit, comprising the motor phase inductances and the parasitic capacitance of converter switches, power cables, and motor phase windings. For salient machines, in general, the associated resonance frequency of the circuit depends on the rotor position. In the position-estimation method, an initial voltage distribution is imposed over the impedances of the resonant circuit after which the circuit is let to oscillate freely. During this phase of free oscillation, the induced voltage over a phase winding exhibits a damped oscillatory behavior, from which position information can be retrieved. An overview is given of the different possibilities to trigger the voltage resonance. It is shown that the proposed position-estimation method has favorable characteristics such as measurement of large-amplitude voltages, robustness against temperature deviations of motor and power semiconductors, very high update rates for the estimated position, and absence of sound and disturbance torque. Experimental results are given for a sensorless commutation scheme of an SRM under small load.

Capacitive sensor system with noise reduction

Abstract: A system for reducing noise when detecting the capacitance value of a capacitor in a touch display that operates in a potentially noisy environment. A capacitance sensor is provided for determining the size of the capacitor in the touch screen display and includes a charging circuit that charges the capacitor and a discharge circuit that resets the charge of the capacitor to substantially zero. A control circuit controls the capacitance sensor and the operation of the charge and discharge circuits in accordance with a predetermined charging/discharging algorithm to resolve the value of the capacitor and output such value in a sampling operation. The operation of the control circuit and the charging/discharging algorithm is subject to errors as a function of the noisy environment, which errors will be reflected in the output value. A noise reduction circuit is provided to modify the operation of the control circuit to reduce noise.

On Two-Phase Switched-Capacitor Multipliers With Minimum Circuit Area

Abstract: This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serial-parallel, linear (LIN), Fibonacci, and 2N multipliers are compared. Results show that the LIN cell is the best for integration because of the smallest total capacitor area and the highest current efficiency under the assumption that the parasitic capacitance is not smaller than 10% of the multiplier capacitance, and the Fibonacci cell is the best for discrete application because of the minimum number of capacitor components with moderate current efficiency under the assumption that the parasitic capacitance is not larger than 1% of the multiplier capacitance.

Self-Aligned-Gate ZnO TFT Circuits

Abstract: We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gate-self-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a selfaligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm2/V · s. The seven-stage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (> 5× longer).

Analysis of small deflection touch mode behavior in capacitive pressure sensors

Abstract: Due to an increasing need for devices with low power consumption, capacitive pressure sensors have become good substitutes for the well known piezoresistive pressure sensors. Mathematical models are necessary to design and characterize the device, preferably the model is analytical such that geometrical scalings are revealed. We show that, in the case of linear elastic behavior, a simple analytical model can be found for a touch mode capacitive pressure sensor (TMCPS). With this model it is possible to readily evaluate the main features of a TMCPS such as: sensitivity (both in normal and touch mode), touch point pressure and parasitic capacitance. Therefore, the desired device can be designed without using finite element modeling (FEM). This reduces the effort needed to design a micromachined TMCPS. Finally, the model has been compared with a micromachined TMCPS showing an excellent agreement with the experimental data.

A New and Fast-Readout Interface for Resistive Chemical Sensors

Abstract: The main issue concerning metal oxide (MOX) gas sensors is mostly related to the wide range of resistive values that the sensors can show. In addition, some sensors could have baseline resistive values up to tens of gigohms. To avoid the use of expensive picoammeters or the use of circuits adopting scaling factors, different solutions have recently been proposed, exploiting the resistance-to-time conversion (RTC) technique. They show good linearity and are suitable for the integration in a chip together with the elaboration unit, but they may require long measurement time (tens of seconds) if high resistance values need to be estimated. In addition, they may suffer the influence of a sensor parasitic capacitance, in parallel with the resistive component. In this paper, a new method is proposed to reduce the measuring time, keeping the advantages offered by the RTC approach and including a parasitic capacitance estimation feature. Particularly, an effective architecture, based on moving thresholds, has been proposed, simulated, and experimentally tested with commercial resistors (values between 1 M? and 100 G?) and capacitors (values between 1 and 47 pF). Finally, a fast sensor transient, due to a rapid change in the heating power, has been acquired with the proposed instrument and compared with a similar transient analyzed with a classical RTC approach. This test has shown the applicability of the interface for solutions requiring detailed information of the sensor response, such as the characterization of new sensors (e.g., nanowires) or the behavior analysis during nonstandard thermal profiles.

Identifying the Bottlenecks to the RF Performance of FinFETs

Abstract: In this work, the high frequency (RF) performance of FinFETs is investigated in detail using a two-level parasitic model comprising outer and inner parasitic capacitances in addition to parasitic series resistances. Use of scaling relations of these parasitic capacitances with numbers of fins and fingers allows extraction of these elements. Next, by defining a series of reference surfaces, each associated with a certain set of parasitic elements, we proceed to calculate the RF Figures of Merit, namely fT and fmax at these surfaces. These are called ‘available fT (fmax)’ in this work. Analysis of the available fT (fmax) gives insight into the extent to which different parasitics affect the FinFET’s RF performance. The main bottleneck to the FinFET’s RF performance is identified, solutions are proposed and relevant trade-offs are discussed.

A 60–110 GHz Transmission-Line Integrated SPDT Switch in 90 nm CMOS Technology

Abstract: This letter demonstrates a fully integrated transmit/receive single-pole-double-throw switch in standard bulk 90 nm CMOS process. This switch is based on the transmission-line integrated approach that reduces the effect of parasitic capacitance of transistors in the desired band, and this approach can achieve good isolation and return loss with fewer stages of transistors and broad bandwidth. The switch provides an insertion loss of 3-4 dB and a return loss better than 10 dB in 60-110 GHz. The measured isolation is better than 25 dB. The measured 1 dB compression point of input power is 10.5 dBm at 75 GHz. To the best of our knowledge, this is the first CMOS switch operating beyond 100 GHz.

A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card

Abstract: An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact memory cards. High speed and low power communication can be performed in the inductive-coupling link because of the removal of highly capacitive ESD protection devices [1]. The wireless interface eliminates mechanical contacts resulting in high reliability. Target data rate is 2.5Gb/s/ch which is 12.5x higher than that of a commercial memory card and target communication range is 0.5mm to 1mm, considering the allowance of card insertion. The maximum data rate of the inductive-coupling link demonstrated in [3] at 1mm distance was 160Mb/s/ch. A theoretical limit is 1Gb/s/ch since self resonant frequency of an on-chip inductor of 3GHz. To increase the self resonant frequency, the inductor is moved off chip to a flexible circuit board to reduce parasitic capacitance. The self resonant frequency of 1mm diameter inductor is increased to 4GHz corresponding to a signal data rate of 1.25Gb/s/ch. Additionally, the number of bit per symbol is increased to 2 by 4 pulse amplitude modulation (4PAM) and a data rate of 2.5Gb/s/ch is achieved. But to communicate by using 4PAM in the inductive-coupling link, issues listed below must be solved. First, the communication range is limited to 0.95mm to 1mm. The amplitude of the received signal is inversely proportional to the communication distance, and therefore, received signal cannot be converted to a correct data without adjusting the input threshold voltages of a receiver. Second, the pulse width is narrower in 4PAM and thus synchronization on the receiver side is difficult.