Showing papers on "Resist published in 2001"

Soft Lithography in Biology and Biochemistry

Abstract: ▪ Abstract Soft lithography, a set of techniques for microfabrication, is based on printing and molding using elastomeric stamps with the patterns of interest in bas-relief. As a technique for fabricating microstructures for biological applications, soft lithography overcomes many of the shortcomings of photolithography. In particular, soft lithography offers the ability to control the molecular structure of surfaces and to pattern the complex molecules relevant to biology, to fabricate channel structures appropriate for microfluidics, and to pattern and manipulate cells. For the relatively large feature sizes used in biology (≥50 μm), production of prototype patterns and structures is convenient, inexpensive, and rapid. Self-assembled monolayers of alkanethiolates on gold are particularly easy to pattern by soft lithography, and they provide exquisite control over surface biochemistry.

Molecular ruler for scaling down nanostructures

Abstract: The present invention is a method and apparatus relating to manufacturing nanostructure patterns and components using molecular science. The method includes overlaying a multilayer organic molecule resist on at least a portion of a parent structure selectively deposited on a substrate, depositing a layer over the parent structure and in contact with at least a portion of the multilayer organic resist, and removing the multilayer organic molecule resist to leave a residual structure.

Polymer, resist composition and patterning process

Abstract: A polymer obtained through copolymerization of a monomer having a hexafluoroalcohol pendant whose hydroxyl moiety has been protected and a monomer having an acid labile group is useful as an additive to a photoresist composition for immersion lithography. When processed by immersion lithography, the resist composition exhibits good water repellency and water slip and produces few development defects.

Immersion lithography at 157 nm

Abstract: We present a preliminary study on the feasibility of immersion lithography at 157 nm for patterning below 70 nm. This technology can enable an enhancement in resolution of ∼40% without radical changes in lasers, optics, or resist technology. We have identified a class of commercially available liquids, perfluoropolyethers, which are good candidates for use as immersion liquids. They are transparent (α≈10−3 μm−1 base 10), optically clean, chemically inert, and compatible with at least some current resist materials and with the semiconductor manufacturing environment. We have also constructed a high-resolution lensless interference immersion lithography system, preserving much of the design of a previous nonimmersion interference system. With this immersion interference tool, we have patterned resist with 30 nm dense features.

Resist material and pattern forming method

Abstract: Provided are a PED-stabilizer-containing resist material having high sensitivity and high resolution, and sufficient PED stability; and a pattern forming method using the resist material. More specifically, the resist material contains at least one compound selected from thiol derivatives, disulfide derivatives and thiolsulfonate derivatives. This resist material may further contain a dissolution inhibitor and/or surfactant. The pattern forming method comprises steps of applying the resist material to a substrate; after a heat treatment, exposing the substrate to a high energy beam or electron beam through a photomask; and after an optional heat treatment, developing the resist material with a developer.

Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect

Abstract: In the invention an electrically isolated copper interconnect structural interface is provided involving a single, about 50-300 A thick, alloy capping layer, that controls diffusion and electromigration of the interconnection components and reduces the overall effective dielectric constant of the interconnect; the capping layer being surrounded by a material referred to in the art as hard mask material that can provide a resist for subsequent reactive ion etching operations, and there is also provided the interdependent process steps involving electroless deposition in the fabrication of the structural interface. The single layer alloy metal barrier in the invention is an alloy of the general type A—X—Y, where A is a metal taken from the group of cobalt (Co) and nickel (Ni), X is a member taken from the group of tungsten (W), tin (Sn), and silicon (Si), and Y is a member taken from the group of phosphorous (P) and boron (B); having a thickness in the range of 50 to 300 Angstroms.

Large area dense nanoscale patterning of arbitrary surfaces

Abstract: We demonstrate a large-area fabrication of hexagonally ordered metal dot arrays with an area density of ∼1011/cm2. We produced 20 nm dots with a 40 nm period by combining block copolymer nanolithography and a trilayer resist technique. A self-assembled spherical-phase block copolymer top layer spontaneously generated the pattern, acting as a template. The pattern was first transferred to a silicon nitride middle layer by reactive ion etch, producing holes. The nitride layer was then used as a mask to further etch into a polyimide bottom layer. The metal dots were produced by an electron beam evaporation followed by a lift-off process. Our method provides a viable route for highly dense nanoscale patterning of different materials on arbitrary surfaces.

Fabrication of <5 nm width lines in poly(methylmethacrylate) resist using a water:isopropyl alcohol developer and ultrasonically-assisted development

Abstract: We report on the fabrication of 3–4 nm wide continuous lines in a positive tone electron beam resist poly(methylmethacrylate) on a solid substrate. This narrow linewidth was made possible through the use of a nonsolvent-based developer system, water:isopropyl alcohol, together with ultrasonically-assisted development, which reduced the effective development time thus limiting the swelling of the unexposed resist. This combination of solvent system and development technique results in a smaller radius of gyration in the developing polymer molecules and in a wider exposure dose latitude compared to conventional processing and so allows ultrasmall features to be reproduced.

Method for forming bump, semiconductor device and method for making the same, circuit board, and electronic device

Abstract: The invention provides a method for readily forming a bump with a desired width, a semiconductor device and a method for making the same, a circuit board, and an electronic device. A method for forming a bump includes forming an opening in an insulating film which exposes at least a part of a pad, and forming the bump so as to be connected to the pad. A resist layer 20 defines a through hole which extends over at least a part of the pad in plan view. A metal layer is formed in the opening so as to connect to the exposed portion of the pad.

Semiconductor device and process of production of same

Abstract: A semiconductor device, in particular a thin semiconductor package, which reduces and simultaneously achieves a uniform mounting height, does not require complicated steps for mounting individual chips, improves the manufacturing yield, achieves a uniform height of the semiconductor device without being affected by the variation in thickness of the chip, and enables execution of an electrical test all together, and a process for production of the same, wherein a semiconductor is mounted, with its back surface exposed upward, on the top surface of an insulating tape substrate having through holes in the thickness direction, the area around the side surfaces of the semiconductor element is sealed by a sealing resin layer, metal interconnections formed on the bottom surface of the tape substrate define the bottom portions of the through holes of the tape substrate, a solder resist layer having through holes in the thickness direction covers the bottom surface of the metal interconnections and the tape substrate, connection terminals extending downward from the active surface of the semiconductor element are inserted into the through holes of the tape substrate, a filler comprised of a conductive material fills the gaps between the connection terminals and the through holes of the tape substrate, and the connection terminals and the metal interconnections are electrically connected

Methods and systems for lithography process control

Abstract: Methods and systems for evaluating and controlling a lithography process are provided. For example, a method for reducing within wafer variation of a critical metric of a lithography process may include measuring at least one property of a resist disposed upon a wafer during the lithography process. A critical metric of a lithography process may include, but may not be limited to, a critical dimension of a feature formed during the lithography process. The method may also include altering at least one parameter of a process module configured to perform a step of the lithography process to reduce within wafer variation of the critical metric. The parameter of the process module may be altered in response to at least the one measured property of the resist.

Study of the resist deformation in nanoimprint lithography

Abstract: Numerical simulations and experimental studies are carried out to understand the deformation process of thin polymer film in nanoimprint lithography. Deformation of a thin polymer above its glass transition temperature is studied for various imprinting conditions such as the aspect ratios of a mold pattern, initial thickness of the polymer, and imprinting pressure. Cross-sectional profiles of the deformed polymers are simulated by the finite element method based on a rubber elastic model. The results are compared with experimental data. The areal penetration ratio of the polymer into the recessed groove of the mold and residual thickness underneath the mold are quantitatively evaluated. The simulations and the experimental results agree well with each other.

Method of design and fabrication of integrated circuits using regular arrays and gratings

Abstract: A circuit fabrication and lithography process utilizes a mask including dense repetitive structures of features that result in a wide array of fine densely populated features on the exposed substrate film. Following this, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate. An optional final step adds additional features as well as the interconnect features thus forming a circuit pattern. In this manner, all fine features may be generated using the exact same density of intensity patterns, and therefore, maximum consistency between features is established without the need for optical proximity correction. The secondary exposures are substantially independent from the initial dense-feature exposure in that the exposure of one set of features and the subsequent exposure of another set of features result in separate independent resist or masking layer reactions, thus minimizing corner rounding, line end shortening and other related spatial frequency effects and unwanted exposure memory effects.

Ester compounds, polymers, resist compositions and patterning process

Abstract: A novel ester compound having an exo-form 2-alkylbicyclo[2.2.1]heptan-2-yl group as the protective group is provided as well as a polymer comprising units of the ester compound. The polymer is used as a base resin to formulate a resist composition having a higher sensitivity, resolution and etching resistance than conventional resist compositions.

Semiconductor device and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To secure large capacitor capacitance by forming capacitors of adjacent memory cells in different layers so that the flat regions in which capacitors are formed are overlapped one another. SOLUTION: After removing the resist, an upper-layer insulation film 19 is formed on the entire surface. An upper-layer contact hole 12 is buried, and at the same time a conductive film is formed so that it covers the entire surface. Next, a resist on which patterning is performed is formed. Using the resist as a mask, the conductive film is etched, and an upper-layer storage 14 is formed. After removing the resist, an upper-layer insulation film 21 is formed on the entire surface. Then, an upper-layer cell plate 20 is formed on the entire surface, and lower-layer capacitor 22 and an upper-layer capacitor 23 are formed. Thus, the capacitors of the adjacent memory cells are formed in different layers so that the flat regions in which the storage nodes of the adjacent capacitors are formed are overlapped one another.

Catalytic amplification of the soft lithographic patterning of Si. Nonelectrochemical orthogonal fabrication of photoluminescent porous Si pixel arrays.

Abstract: Photoluminescent, porous silicon pixel arrays were fabricated via a Pt-promoted wet etching of p-type Si(100) using a 1:1:1 EtOH/HF/H2O2 solution. The pixels were fabricated with micrometer-scale design rules on a silicon substrate that had been modified with an octadecyltrichlorosilane (OTS) monolayer patterned using microcontact printing. The printed OTS layer serves as an orthogonal resist template for the deposition of a Pt(0) complex, which preferentially deposits metal species in areas not covered with OTS. The Pt centers generate a localized oxidative dissolution process that pits the Si in the Pt-coated regions, resulting in the formation of a porous silicon microstructure that luminesces around 580 nm upon illumination with a UV source. Scanning electron microscopy and fluorescence microscopy images of the fabricated porous silicon structures showed that features in the size range of ∼10−150 μm, and possibly smaller, can be generated by this catalytically amplified soft lithographic patterning me...

Investigation of Approaches for the Fabrication of Protein Patterns by Scanning Probe Lithography

Abstract: This paper investigates three different approaches to patterning proteins within ultrathin resist layers formed from self-assembled monolayers using scanning probe lithography (SPL) at the submicrometer length scale. The first approach uses a “nanografting” method to pattern a reactive carboxylic acid terminated thiol into a resist composed of a methyl-terminated monolayer. Rabbit IgG antigen is bound to the patterned region, and an immunoassay utilizing direct readout of the topographic change resulting from specific binding of anti-rabbit IgG antibody is performed using scanning force microscopy. To address issues related to nonspecific protein adsorption, the other two approaches investigated the patterned removal of glycol-terminated monolayers by mechanically “scraping” patterns at high tip−sample forces by SPL. Protein attachment to the scraped regions was achieved either through the chemisorption of a disulfide coupling agent or by the direct adsorption of Fab‘-SH antibody fragments. Results obtain...

Advanced photoresist technologies for microsystems

Abstract: A growing interest in the development of high aspect ratio photoresists for micromachining microsystems (MST) products has resulted in the availability of a number of commercially available photoresist products. This paper describes in detail the applications of three such resists, namely EPON SU-8, Clariant AZ 4562 and the Shipley electroplated photoresist ED2100. Applications such as etch hard masks, micromoulds, severe topography coatings for metal interconnects and photoplastic mouldings are discussed, and novel examples are presented of where these resists are currently used in both telecomm and microfluidic markets. In particular, the versatility of the photoplastic negative resist EPON SU-8, which is used in a number of MST prototypes, is demonstrated. Future trends in resist technologies for MST are discussed.

Film forming method and film forming apparatus

Abstract: A solvent of a resist solution is dropped from a solvent supply nozzle onto the surface of a semiconductor wafer held by a spin chuck. The semiconductor wafer is rotated by the spin chuck to spread the resist solution over the entire surface of the semiconductor wafer W. Simultaneously, the resist solution is dropped from a resist solution supply nozzle onto the semiconductor wafer and spread following the solvent. During the processing, the processing space is isolated from the outer atmosphere by closing a lid of a processing vessel and a sprayed solvent is supplied into the processing space. The processing space is thus filled with the mist of solvent. In the processing space supplied with the solvent, evaporation of the solvent from the resist solution is suppressed. A film of the resist solution is formed with a uniform film thickness to the edge of the semiconductor wafer W.

Antenna coil for IC card and manufacturing method thereof

Abstract: An antenna coil for an IC card includes a base material of a resin film having the thickness of at least 15 μm and at most 70 μm, and a circuit pattern layer formed on a surface of the base material, having the thickness of at least 7 μm and at most 60 μm formed of an aluminum foil containing aluminum by at least 975 mass % and at most 997 mass % On the surface of the resin film base material, an aluminum foil containing aluminum is fixed by using a polyurethane based adhesive layer containing an epoxy resin, a resist ink layer having a prescribed pattern is printed on the foil, the foil is etched using the resist ink layer as a mask to form a circuit pattern layer, and the resist ink layer is removed

Multilevel nanoimprint lithography with submicron alignment over 4 in. Si wafers

Abstract: We demonstrate that multilevel nanoimprint lithography (NIL) with submicron alignment over an entire 4 in Si wafer can be achieved Average alignment accuracy of 1 μm with a standard deviation 04 μm in both X and Y directions was obtained in ten consecutive tests of multilevel NIL The multilevel alignment was achieved by aligning the wafer and the mask with an aligner, fixing them with a holder, and imprinting in an imprint machine The issues that are critical to the alignment accuracy, such as relative movement during the press, relative thermal expansion, wafer bending, and resist, are discussed The alignment accuracy currently achieved on the system is limited by the aligning accuracy of the aligner, instead of the process of multilevel NIL

Patterning, electroplating and removal of SU-8 moulds by excimer laser micromachining

Abstract: The ablation characteristics of the SU-8 photoresist (spun on Si wafers) under 248 KrF excimer pulsed laser radiation have been studied The variation of etch rate with fluence has been investigated in the range 005-301 J cm-2 The threshold fluence for ablation of SU-8 is measured to be about 005 J cm-2 The etch rate of SU-8 is found to be higher than that of polyimide (previously reported) under similar conditions We have investigated the effects of different prebake temperatures (90, 110, 120 and 200 °C) on ablation characteristics, which are found to be similar for all temperatures The effect of increasing the number of laser shots (from 10 to 10 000) has been examined at different fluences in order to understand the etch-rate variation near the `end of film' stage of ablation The results of our analysis using scanning electron microscopy, profilometry and optical microscopy reveal the very smooth morphology of the etched surfaces with no significant debris, no noticeable damage to underlying silicon and the gradual build-up of a carbonaceous film outside and around the etch pits We find SU-8 very suitable for excimer ablation lithography and have demonstrated this by patterning a gear structure in an SU-8 resist layer with an aspect ratio of 45 For the first time, we have shown that the laser micromachining technique has the potential to cleanly remove SU-8 after electroplating a microstructure with copper

Nanoimprint lithography with a commercial 4-in. bond system for hot embossing

Abstract: In order to examine the suitability of nanoimprinting for wafer scale pattern definition, a commercially available hot embossing system, the EV520HE of EVGroup, Austria, has been used to imprint 4 inch substrates. The EV520HE is based on a production-proven wafer bonding system which guarantees compatibility with semiconductor fabrication conditions. A 4 inch silicon wafer fully patterned with structures from 400 nm to 100 micrometers size was used as a stamp. The patterns, having a nominal height of 260 nm were defined in poly-Si over SiO2 by reactive ion etching. Different anti- sticking layers were applied to the stamps by monolayer self-assembling, among them (1,1,2,2 H perfluoroctyl)- trichlorosilane. Two different polymers, polymethylmethacrylate (PMMA) and a commercially available nanoimprint resist were used to spin-coat the substrates. Imprints were performed with temperatures of up to 225 degree(s)C, forces between 10 bar and 55 bar and holding times of 5 and 15 minutes. After separation of stamp and sample the imprints were characterized by a surface profiler and inspected by an optical microscope as well as a scanning electron microscope. Different qualities of pattern transfer according to the used process parameters were achieved, but patterning of the whole sample surface was always observed. In contrast to radiation-based lithography, the difficulties are based in imprinting of larger features whereas structures of 400 nm size were reproduced with high quality. Therefore the largest patterns of the stamp, 100 micrometers square bond pads, were used for imprint quality assessment, judged by the degree of stamp cavity filling around the pads. High quality was achieved by embossing at 225 degree(s)C with a hold time of 5 minutes at a pressure of 55 bar. For full wafer imprint only a small degradation of imprint quality from the center towards the periphery was observed. Further optimization of the process is required to minimize residual layer thickness for the hot embossing lithography step, taking into account the visco-elastic properties of the polymer material.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Chemical feature doubling process

Abstract: In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.

Semiconductor device provided with semiconductor circuit made of semiconductor element and method of fabricating the same

Abstract: This invention improves TFT characteristics by making an interface between an active layer, especially a region forming a channel formation region and an insulating film excellent, and provides a semiconductor device provided with a semiconductor circuit made of a semiconductor element having uniform characteristics and a method of fabricating the same. In order to achieve the object, a gate wiring line is formed on a substrate or an under film, a gate insulating film, an initial semiconductor film, and an insulating film are formed into a laminate without exposing them to the atmosphere, and after the initial semiconductor film is crystallized by irradiation of infrared light or ultraviolet light (laser light) through the insulating film, patterning is carried out to obtain an active layer and a protection film each having a desired shape, and then, a resist mask is used to fabricate the semiconductor device provided with an LDD structure.

Method for forming pattern

Abstract: A method of forming a pattern, which comprises forming a masking material layer on a surface of a working film by coating the surface with a solution of a mixture comprising an inorganic compound having a bond between an inorganic element and oxygen atom, and a volatile unit, volatilizing the volatile unit to thereby make the masking material layer porous, forming a resist layer on a surface of the masking material layer, patterning the resist film to form a resist pattern, dry-etching the masking material layer to thereby transfer the resist pattern to the masking material layer, thereby forming a masking material pattern, and dry etching the working film to thereby transfer the masking material pattern to the working film to thereby form a working film pattern.

Stereolithographic patterning with interlayer surface modifications

Abstract: Methods for the preparation of multilayered resists include exposure of the a first layer to radiation followed by exposure to an oxidizing agent. The oxidizing agent alters the surface characteristics of the first resist layer such that it is rendered more hydrophilic than the original resist layer. A second layer of resist is then applied to the oxidized surface of the first resist layer and exposed to radiation. This process can be repeated for thousands of coating layers, thereby permitting stereolithographic patterning of parts and construction of micromachines. A final treatment with a dissolution solution will dissolve unwanted resist material. Dependent upon the type of resist material used in the multilayered resist, the dissolution solution can remove the radiation exposed areas, e.g., a positive resist, or remove unexposed areas, e.g., a negative resist.

Ultra-fine machining tool/molds by LIGA technology

Abstract: Machining tools based on the excimer laser and x-ray lithography to make ultra-fine machining tool/molds are described in this paper. The lower high-aspect ratio resist molds are fabricated using the KrF excimer laser. The higher aspect-ratio resist molds are made using x-ray lithography. Both low and high aspect-ratio resist molds are then converted into metallic structures using electroforming. The NiCo/SiC microcomposite electroforming with low internal stress (~0 kg mm-2) and high hardness (>Hv500) shows its feasibility as mold materials. An example of 2 mm thick integrated circuit (IC) packaging leadframe patterns using x-ray micromachining is illustrated to prove its feasible application. On the technical side, micro-structures with a high aspect ratio of 30 were developed using a graphite membrane based x-ray mask.