Showing papers on "Subthreshold conduction published in 1993"

Scaling theory for double-gate SOI MOSFET's

Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Three-dimensional "atomistic" simulation of discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's

Abstract: In this paper, discrete random dopant distribution effects in sub-0.1 /spl mu/m MOSFET's were studied using three-dimensional drift-diffusion "atomistic" simulations. Effects due to the random fluctuation of the number of dopants in the MOSFET channel and the microscopic random distribution of dopant atoms in the MOSFET channel were investigated. We found that, in addition to the well-known fluctuation of the threshold voltage, there was an average shift of the threshold voltage to a lower value. The average shift was believed to be attributed to the inhomogeneity of channel potential due to the discreteness of channel dopants, and the logarithmic dependence of subthreshold current. Microscopic dopant distribution also gave rise to asymmetry in drain current upon interchanging the source and the drain. >

Ionic mechanisms for the subthreshold oscillations and differential electroresponsiveness of medial entorhinal cortex layer II neurons

Abstract: 1. Layer II of the medial entorhinal cortex is composed of two electrophysiologically and morphologically distinct types of projection neurons: stellate cells (SCs), which are distinguished by rhythmic subthreshold oscillatory activity, and non-SCs. The ionic mechanisms underlying their differential electroresponsiveness, particularly in the subthreshold range of membrane potentials, were investigated in an "in vitro" slice preparation. 2. In both SCs and non-SCs, the apparent membrane input resistance was markedly voltage dependent, respectively decreasing or increasing at hyperpolarized or subthreshold depolarized potential levels. Thus the neurons displayed inward rectification in the hyperpolarizing and depolarizing range. 3. In the depolarizing range, inward rectification was blocked by tetrodotoxin (TTX, 1 microM) in both types of neurons and thus shown to depend on the presence of a persistent low-threshold Na+ conductance (gNap). However, in the presence of TTX, pronounced outward rectification became manifest in the subthreshold depolarizing range of membrane potentials (positive to -60 mV) in the SCs but not in the non-SCs. 4. The rhythmic subthreshold membrane potential oscillations that were present only in the SCs were abolished by TTX and not by Ca2+ conductance block with Cd2+ or Co2+. Subthreshold oscillations thus rely on the activation of voltage-gated Na+, and not Ca2+, conductances. The Ca2+ conductance block also had no effect on the subthreshold outward rectification. 5. Prominent time-dependent inward rectification in the hyperpolarizing range in the SCs persisted after Na(+)- and Ca2+ conductance block. This rectification was not affected by Ba2+ (1 mM), but was blocked by Cs+ (1-4 mM). Therefore, it is most probably generated by a hyperpolarization-activated cationic current (Q-like current). However, the Q-like current appears to play no major role in the generation of subthreshold rhythmic membrane potential oscillations, because these persisted in the presence of Cs+. 6. On the other hand, in the SCs, the fast, sustained, outward rectification that strongly developed (after Na+ conductance block) at the oscillatory voltage level was not affected by Cs+ but was blocked by Ba2+ (1 mM). Barium was also effective in blocking the subthreshold membrane potential oscillations. 7. In the non-SCs, which do not generate subthreshold rhythmic membrane potential oscillations or manifest subthreshold outward rectification in TTX, Ca2+ conductance block abolished spike repolarization and caused the development of long-lasting Na(+)-dependent plateau potentials at a high suprathreshold voltage level. At this level, where prominent delayed rectification is present, the Na+ plateaus sustained rhythmic membrane potential oscillations.(ABSTRACT TRUNCATED AT 400 WORDS)

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Abstract: A switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of subthreshold current with threshold-voltage scaling. Inserting a switched impedance at the source of a MOS transistor reduces the standby subthreshold current of giga-scale LSI's operating at room temperature by three to four orders of magnitude and suppresses the current variation caused by threshold-voltage and temperature fluctuations. The scheme is applicable to any combinational and sequential CMOS logic circuits as long as their standby node voltages are predictable. The standby current of a 16-Gb DRAM is expected to be reduced from 1.1 A to 0.29 mA using this scheme. Hence, battery backup of giga-scale LSI's will be possible even at room temperature and above. >

Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs

Abstract: An analytical model for the subthreshold regime of operation of short-channel MOSFETs is presented, and expressions for the threshold-voltage shift associated with the drain-induced barrier lowering (DIBL) caused by the application of a drain bias are developed. The amount of drain-bias-induced depletion charge in the channel is estimated, and an expression for the distribution of this charge along the channel is developed. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized unified charge control model (UCCM) for short-channel MOSFETs are presented. The theory is applicable to deep-submicrometer devices with gate lengths larger than 0.1 mu m. The model is suitable for implementation in circuit simulators. >

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)

Abstract: Analytical expressions are presented for subthreshold current reduction in a decoded-driver by self-reverse biasing, which is inherently required for low-voltage, low-power, high-speed DRAM's for portable equipment. The scheme involves inserting a switching MOS transistor between the driver circuits and its power supply line. The subthreshold current of the decoded-driver is reduced to the order of 10/sup -3/ in the practical temperature range (250-350 K) with 254 mV of self-reverse biasing voltage, while the delay time is only 3% more than in conventional schemes. The transition time of 1 ms from the operating state to the low subthreshold current state is sufficient to reduce the subthreshold current. The rapid recovery time of 1 ns from the low subthreshold current state does not interrupt the start of normal operation. The subthreshold current reduction was confirmed experimentally using a test chip fabricated with 0.25- mu m technology. >

An analytical expression for sheet carrier concentration vs gate voltage for HEMT modelling

Abstract: A simple expression of the Fermi potential ( E F ) variation with the sheet carrier concentration ( n s ) in the two-dimensional electron gas at the heterojunction of a High Electron Mobility Transistor (HEMT) is presented This particular approximation is shown to lead to an analytical expression for n s in termks of the applied gate voltage ( V G ) Comparisons with the exact solutions of n s vs E F and n s vs V G as well as with several previous approximations show that our results are more accurate for a wider range of values of n s at different temperatures This single analytical expression for n s as a function of V G , valid from subthreshold to high conduction, can be used for better analytical modelling of HEMTs

Experimental Study Of Threshold Voltage Fluctuations Using An 8k MOSFET's Array

Abstract: Increasing the number of transistors and scaling down the dimensions of the transistors in ULSIs are considered to enhance the fluctuations of the transistor characteristics, from the viewpoint of the channel doping fluctuations [l], 121. However, the statistical study of the transistor fluctuations has not been experimentally performed. In this paper, we have focussed on the threshold voltage V,, fluctuatioris of 8k NMOSFET’s in a less than 0.8mm2 area, using a newly developed 256x32 transistor array with a 8bit binary counter. It is experimentally shown for the first time that the V,, fluctuatioris depend on the channel length and the gate oxide thiclmess. Furthermore, it is directly demonstrated that the V,, fluctuations correlate with the dopant number fluctuations of the channel region.

Critical behavior of charge-density waves below threshold: Numerical and scaling analysis.

Abstract: The critical behavior of pinned charge-density waves (CDW's) is studied as the threshold for sliding is approached. Using the Fukuyama-Lee-Rice Hamiltonian with relaxational dynamics, the polarization and linear response are calculated numerically. Analytic bounds on the subthreshold motion are used to develop fast numerical algorithms for evolving the CDW configuration. Two approaches to threshold, reversible and irreversible, are studied, which differ in the details of the critical behavior. On the irreversible approach to threshold, the response due to avalanches triggered by local instabilities dominates the polarizability, which diverges in one and two dimensions

On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

Abstract: A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson's equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator. >

Simulation and two-dimensional analytical modeling of subthreshold slope in ultrathin-film SOI MOSFETs down to 0.1 mu m gate length

Abstract: The subthreshold slope in ultra-thin-film fully depleted SOI MOSFETs is investigated for channel lengths from the long channel region down to 0.1 mu m. A doping effect is found which allows improvement of the S-factor by increasing the channel doping concentration. In order to explain this phenomenon and to clarify the mechanism of S-factor degradation at short gate lengths, a two-dimensional analytical model is developed. A modified boundary condition for the two-dimensional Poisson equation is introduced to account for the nonlinear potential distribution inside the buried oxide. It is found that the S-factor short-channel degradation is governed by three mechanisms: the rise of capacitances at the channel source and drain ends due to the two-dimensional potentional distribution; the subthreshold current flow at the back channel surface; and the modulation of the effective current channel thickness during the gate voltage swing in the subthreshold region. The analytical model results are compared to those of numerical device simulation, and a good agreement is found. >

256-Mb DRAM circuit technologies for file applications

Abstract: 256-Mb DRAM circuit technologies characterized by low power and high fabrication yield for file applications are described. The newly proposed and developed circuits are a self-reverse-biasing circuit for word drivers and decoders to suppress the subthreshold current to 3% of the conventional scheme, and a subarray-replacement redundancy technique that doubles chip yield and consequently reduces manufacturing costs. An experimental 256-Mb DRAM has been designed and fabricated by combining the proposed circuit techniques and a 0.25- mu m phase-shift optical lithography, and its basic operations are verified. A 0.72- mu m/sup 2/ double-cylindrical recessed stacked-capacitor (RSTC) cell is used to ensure a storage capacitance of 25 fF/cell. A typical access time under a 2-V power supply voltage was 70 ns. With the proper device characteristics, the simulated performances of the 256-Mb DRAM operating with a 1.5-V power supply voltage are a data-retention current of 53 mu A and an access time of 48 ns. >

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

Abstract: We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics. >

Effects of total-dose irradiation on gate-all-around (GAA) devices

Abstract: The response of gate-all-around (GAA) MOS transistors to dose irradiation is quite different from that observed on other types of silicon-on-insulator (SOI) MOSFETs. In regular SOI MOSFETs, edge leakage increases substantially faster than the main transistor leakage upon creation of oxide charges due to the irradiation. The GAA MOSFET behaves in the opposite way; the shift of edge threshold voltage upon creation of charges in the oxide is smaller than that of the main transistor. As a result, a kink develops in the subthreshold characteristics of regular SOI MOSFETs upon irradiation, while the original subthreshold kink of GAA devices disappears when the device is irradiated. >

Subthreshold-current reduction circuits for multi-gigabit DRAM's

Abstract: Subthreshold-current reduction, especially at room-temperature operation, is one of the key design issues in the gigabit era. Despite its importance, however, a scheme for it has not been proposed. In this paper, innovative circuits featuring a hierarchical power-line scheme and a switched-power-supply CMOS inverter with a level holder are proposed. They can drastically reduce even the active current of a 16 Gbit DRAM by one tenth, from 1.2A to 116mA.

A table lookup FET model for accurate analog circuit simulation

Abstract: A table-based approach to the empirical modeling off FETs in circuit simulators addresses the specific requirements of analog circuit design, such as accuracy in reproducing small-signal parameters, large signal nonlinearities, subthreshold characteristics, substrate effects, short-channel effects, and voltage dependent capacitances. Efficiencies in storage and computation brought about by this model in SPICE considerably speed up circuit simulation, compared to an analytical model offering similar accuracy. Methods are described to extract the table entries. The model is not specific to any one type of device or technology, although examples are given of how it may be simplified by using physical insights into device operation. >

256 Mb DRAM technologies for file applications

Abstract: The authors describe 256-Mb DRAM (dynamic random access memory) technologies for file applications. A subthreshold-current limiting scheme for word drivers is shown. The scheme uses a pMOS switching transistor between the wordline voltage and the driver transistor common-source terminal. The subthreshold current of a 256-Mb DRAM is reduced to 3% by applying this scheme to word drivers and decoders, and the total data-retention current is less than that of a 64-Mb DRAM. A redundancy technique is shown which features subarray-by-subarray replacement instead of the conventional line-by-line replacement. To evaluate the circuit technologies described here, an experimental 256-Mb DRAM was fabricated using 0.25- mu m CMOS technology with phase-shift lithography. It uses a 0.72- mu m/sup 2/ RSTC cell with a storage capacitance of 25 fF and operates on a voltage of 1.5-3.6 V. >

Linear tunable COMFET transconductor

Abstract: A linear tunable transconductor is designed with the use of linear COMposite n-channel MOSFETs (COMFETs) and CMOS COMposite FETs as basic cells. With crosscoupling, a differential linear relation is achieved with a THD at 1 kHz of 0.776% for a differential voltage of +or-4 V. The design of the transconductor demonstrates that COMFET devices can be successfully used as standard cells in modulator analogue VLSI circuits. The transconductor performance at subthreshold is also discussed.< >

Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface

Abstract: A semiconductor structure with germanium implant is provided for reducing VT shifts at the channel edges thereby minimizing short channel effects and subthreshold currents at or near the substrate surface. The semiconductor structure is adapted to receive non-perpendicular implant of germanium in the juncture between the channel and the source/drain regions as well as in the juncture between field oxide channel stop implant and source/drain regions. By carefully and controllably placing the germanium at select channel and field regions, segregation and redistribution of threshold adjust implant and channel stop implant dopant materials is substantially minimized. Reducing the redistribution of such materials provides a reduction in the short channel effects and, particularly, a reduction in substrate surface current or DIBL-induced current.

An analog implementation of early visual processing in insects

Abstract: An analog VLSI implementation which mimics the early visual processing stages in insects is described. The system is composed of sixty parallel channels of integrated photodetectors and processing elements. It serves as the front end processor for a motion detection chip. The photodetection circuitry includes p-well junction diodes on a 2 mu m CMOS process and a logarithmic compression to increase the dynamic range of the system. The processing elements consist of an analog differentiator behind each photodetector. The differentiators are low frequency and have been designed using subthreshold design methods. >

Short-channel effects and drain-induced barrier lowering in nanometer-scale GaAs MESFET's

Abstract: Short-channel effects in GaAs MESFETs are investigated. MESFETs were fabricated with gate lengths in the range of 40 to 300 nm with GaAs and AlGaAs buffer layers. The MESFETs were characterized by DC transconductance, output conductance, and subthreshold measurements. This work focuses on overcoming the short-channel effect of large output conductance by the inclusion of an AlGaAs buffer layer, and identifying the benefit the AlGaAs buffer affords for reducing subthreshold current, including the effect of drain-induced barrier lowering. The design yielded 300-nm gate-length MESFETs with excellent suppression of the major short-channel effects. >

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's

Abstract: The reduction of exponentially increasing standby subthreshold current due to threshold-voltage (V/sub T/) scaling is one of the most important design issues for giga-scale LSIs operating at room temperature This paper proposes a switched-source-impedance CMOS circuit featuring the subthreshold current reduction of LSIs in standby mode by 34 decades with minimum speed penalty in active mode The circuit also features V/sub T/ variation immunity due to the negative feedback effect through the source impedance This scheme permits battery backup even for giga-scale LSIs

Opportunities for Scaling FET's for Gigascale Integration (GSI)

Abstract: Using two-and three dimensional analytical and numerical models, scaling limits derived from small-geometry degradation of subthreshold characteristics are compared for six different FET structures in bulk Si, SOI and GaAs technologies For Si devices, the low impurity channel MOSFET can be scaled down to L min = 0045?m and the dual gate SOI MOSFET to L min = 0028?m The GaAs MESFET can be scaled to L min = 013?m and the AlGaAs/GaAs MODFET to 0095?m The key physical effect which enables small values of L min is the relative strength of the coupling between the gate and channel charge distributions

An analytical threshold voltage and subthreshold current model for short-channel MESFETs

Abstract: Short-channel effects on the subthreshold behavior are modeled in self-aligned gate MESFETs with undoped substrates through an analytical solution of the two-dimensional Poisson equation in the subthreshold region. Based on the resultant potential solution, simple and accurate analytical expressions for short-channel threshold voltage, subthreshold swing, and subthreshold drain current are derived. These are then used to develop an expression for minimum acceptable channel length. A comparative study of the short-channel effects in MESFETs with doped and undoped substrates indicates that channel lengths will be limited to 0.15-0.2 mu m by subthreshold conduction. Besides offering insight into the device physics of the short-channel effects in MESFETs, the model provides a useful basis for accurate analysis and simulation of small-geometry GaAs MESFET digital circuits. >

Semiconductor memory driven at low voltage

Abstract: The signal levels of a plurality of word lines (high and low) are controlled by outputs of upper address decoders and a lower address decoder. Each of the upper address decoders, when it is selected, supplies a word line control signal from the lower address decoder to all the word lines. The word line control signal is used to supply a high voltage only to one word line and a ground potential to other word lines. On the other hand, when the upper address decoder is not selected, it supplies a nonselection level voltage from a low voltage generator. This voltage is lower than the ground potential. Thus, the voltage is applied to the gates of transfer gates connected to the word lines, thereby suppressing a subthreshold current to a small value, thereby decreasing a leakage current from memory cells.

Analytical Models for Symmetric Thin-Film Double-Gate Silicon-on-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistors

Abstract: We derived analytical models for the current-voltage characteristics of double-gate silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors. In the subthreshold region, we derived an analytical subthreshold slope model considering both depleted and induced charges. We proposed a unique definition of threshold voltage of the device, and showed that the threshold voltage is close to the experimentally defined threshold voltage at which the drain current has a specific value. The variation in the surface potential after the threshold voltage was modeled, and hence the models are valid in the moderate-inversion region as well as in the strong-inversion region. The models agree well with experimental data.

Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAMs

Abstract: Two-dimensional power-line selection scheme for an iterative CMOS circuit block, is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks of two-dimensional arrangement and selectively energized by two-dimensional power-line selection. The scheme combined with dual word-line structure permits a drastic active current reduction to one sixteenth, from 363 mA to 22 mA, for a 16-Gb DRAM.

Power-on reset circuit having a low static power consumption

Abstract: A power-on reset circuit which employs a supply voltage sensing branch for triggering a first inverter of a pair of cascaded inverters. The intrinsic static consumption of such a POR circuit is strongly reduced by employing a current generator, which is automatically forced to deliver a reduced current during the operation of the integrated circuit, for biasing two transistors functionally connected in said voltage sensing branch into a subthreshold operating condition.

Unified quasi-static MOSFET capacitance model

Abstract: An accurate calculation of MOSFET capacitance-voltage (C-V) characteristics has to account for the bulk charge which is affected by nonuniform doping profiles and short-channel effects. In an approach based on the unified charge control model (UCCM), the voltage dependencies of the bulk charge are related to the standard parameters of the body plots which are routinely measured during MOSFET characterization. The results of the C-V calculations based on this model are in good agreement with experimental data and calculations based on the standard BSIM model. Compared to the BSIM simulations, the present model more accurately describes capacitances related to the bulk charge and the device subthreshold behavior, and it is suitable for incorporation into circuit simulators. >

Drain-induced barrier lowering in buried-channel MOSFET's

Abstract: In the literature, it is unclear whether or not buried-channel (BC) MOSFETs are less resistant to drain-induced barrier lowering than surface-channel MOSFETs. The authors clarify this confusion and experimentally demonstrate the relationship between the threshold voltage and channel length reduction for normally-on (inverting) BC-MOSFETs. The results are compared with similar measurements on surface-channel MOSFETs. It is shown that BC-MOSFETs are more prone to drain-induced barrier lowering than surface-channel MOSFETs. A simple analytic model is derived for the subthreshold current in small-geometry BC-MOSFETs. The model shows good agreement with experimental measurements and with subthreshold currents obtained using a two-dimensional numerical simulator. >