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Robert M. Wallace

Researcher at University of Texas at Dallas

Publications -  503
Citations -  41237

Robert M. Wallace is an academic researcher from University of Texas at Dallas. The author has contributed to research in topics: X-ray photoelectron spectroscopy & Atomic layer deposition. The author has an hindex of 84, co-authored 499 publications receiving 37236 citations. Previous affiliations of Robert M. Wallace include Texas Instruments & University of Texas System.

Papers
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Accumulation capacitance frequency dispersion of III-V metal-insulator-semiconductor devices due to disorder induced gap states

TL;DR: In this paper, the origin of anomalous frequency dispersion in accumulation capacitance of metal-insulator-semiconductor devices on InGaAs and InP substrates was investigated using modeling, electrical characterization, and chemical characterization.
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A novel thermally-stable zirconium amidinate ALD precursor for ZrO2 thin films

TL;DR: ZrO"2 thin films were deposited by the atomic layer deposition process on Si substrates using tetrakis(N,N'-dimethylacetamidinate) zirconium (Zr-AMD) as a Zr precursor and H"2O as an oxidizing agent as mentioned in this paper.
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Contact Engineering High-Performance n-Type MoTe2 Transistors.

TL;DR: Unipolar n-type MoTe2 transistors with the highest performance to date are demonstrated, including high saturation current and relatively low contact resistance and high resolution X-ray photoelectron spectroscopy reveals that interfacial metal-Te compounds dominate the contact resistance.
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Interface studies of GaAs metal-oxide-semiconductor structures using atomic-layer-deposited HfO2/Al2O3 nanolaminate gate dielectric

TL;DR: In this article, a systematic capacitance-voltage study has been performed on GaAs metal-oxide-semiconductor (MOS) structures with atomic layer-deposited HfO2∕Al2O3 nanolaminates as gate dielectrics.
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Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance - voltage analysis

TL;DR: In this article, border traps and interface traps in HfO2/few-layer MoS2 top-gate stacks are investigated by C-V characterization, and the border traps are associated with the dielectric, likely a consequence of low-temperature deposition.