Journal ArticleDOI
An MOS transistor model for analog circuit design
TLDR
A physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits is presented.Abstract:
This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model.read more
Citations
More filters
Journal ArticleDOI
Nanopower OTAs With Improved Linearity and Low Input Offset Using Bulk Degeneration
TL;DR: A circuit implementing the full signal conditioning of a piezoelectric accelerometer for adaptive pacemakers is presented, as an application example of the proposed OTA combining both source and bulk degeneration to achieve an increased linear range above 1 V.
Journal ArticleDOI
Improved analytical modeling of polysilicon depletion in MOSFETs for circuit simulation
TL;DR: In this paper, a new approach to analytically modeling the polysilicon depletion effect on drain current and transconductances as well as node charges and transcapacitances is presented.
Journal ArticleDOI
Analog circuit design using graded-channel silicon-on-insulator nMOSFETs
TL;DR: In this paper, an extended study of analog circuit design using graded-channel (GC) silicon-on-insulator (SOI) MOSFETs in comparison to conventional fully depleted (1713) transistors is performed.
The EKV 3.0 Compact MOS Transistor Model: Accounting for Deep-Submicron Aspects
Matthias Bucher,Christian Enz,Francois Krummenacher,J.-M. Sallese,Christophe Lallement,A.-S. Porret +5 more
TL;DR: This research presents a probabilistic procedure for estimating the EKV-NQS response time step-by-step in the aftermath of an electrical shock to the response of the immune system.
Journal ArticleDOI
Resizing rules for MOS analog-design reuse
TL;DR: The procedure presented, designers can calculate parameters for a given circuit in a new technology, starting from the same design in an earlier technology, with simple resizing rules.
References
More filters
Book
Operation and modeling of the MOS transistor
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Journal ArticleDOI
An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications
TL;DR: In this article, a fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented, which exploits the inherent symmetry of the device by referring all the voltages to the local substrate.
Journal ArticleDOI
A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.
Journal ArticleDOI
A charge-sheet model of the MOSFET
TL;DR: In this paper, the authors compared the Pao-Sah double-integral model with the charge sheet model for long-channel MOSFETs and found that the charge-sheet model is simpler to extend to two or three dimensions.