Proceedings ArticleDOI
Performance Investigation of a p-Channel Hetero-Junction GaN Tunnel FET
Manas Ranjan Tripathy,Ashish Kumar Singh,A Samad,Sweta Chander,Prince Kumar Singh,Kamalaksha Baral,Deepak Kumar Jarwal,Ashwini Kumar Mishra,Satyabrata Jit +8 more
TLDR
In this article, a vertical p-channel heterojunction GaN tunnel field effect transistor (TFET) has been reported, where a thin layer of InGaN is filled in between source and channel to enhance the performance of the device.Abstract:
In this work a vertical p-channel heterojunction GaN tunnel field effect transistor (TFET) has been reported. A thin layer of InGaN is filled in between source and channel to enhance the performance of the device. The mechanism of current conduction in the proposed device is based on the physics related to polarization charge induced in III-nitrides compound semiconductor such as GaN, InN, AlN etc. The effect of polarization increases the electric field at the source-channel interface, which opens the door for unidirectional tunneling depending on the voltage applied across gate to source terminal. The other significance of this polarization concept is to reduce the tunneling width in comparison to conventional TFET as well as to minimize ambipolar current. The performance in terms of I ON /I OFF and SS are also investigated for the proposed device.read more
Citations
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Journal ArticleDOI
Impact of interface trap charges on electrical performance characteristics of a source pocket engineered Ge/Si heterojunction vertical TFET with HfO2/Al2O3 laterally stacked gate oxide
Manas Ranjan Tripathy,A Samad,Ashish Kumar Singh,Prince Kumar Singh,Kamalaksha Baral,Ashwini Kumar Mishra,Satyabrata Jit +6 more
TL;DR: In this paper, the impact of interface trap charges (ITCs) on the electrical performance characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET (V-TFET) with an HfO2/Al2O3 laterally stacked heterogeneous gate oxide (LSHGO) structure was reported.
Proceedings ArticleDOI
Device and Circuit-Level Performance Comparison of Vertically Grown All-Si and Ge/Si Hetero-Junction TFET
Manas Ranjan Tripathy,A Samad,Ashish Kumar Singh,Prince Kumar Singh,Kamalaksha Baral,Satyabrata Jit +5 more
TL;DR: In this paper, a Ge/Si heterojunction vertical tunnel field effect transistor (TFET) and All-Si vertical TFET were compared with the conventional Ge-Si TFET using SILVACO ATLASTM TCAD tool.
References
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Journal ArticleDOI
Tunnel field-effect transistors as energy-efficient electronic switches
Adrian M. Ionescu,Heike Riel +1 more
TL;DR: Tunnels based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal–oxide–semiconductor transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.
Journal ArticleDOI
Tunnel Field-Effect Transistors: State-of-the-Art
Hao Lu,Alan Seabaugh +1 more
TL;DR: In this paper, the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology.
Journal ArticleDOI
Heavy doping effects in Mg-doped GaN
Peter Kozodoy,Huili Xing,Steven P. DenBaars,Umesh K. Mishra,Adam William Saxler,R. Perrin,Said Elhamri,W. C. Mitchel +7 more
TL;DR: In this paper, the electrical properties of p-type Mg-doped GaN were investigated through variable-temperature Hall effect measurements, and the measured doping efficiency drops in samples with Mg concentration above 2×1020 cm−3.
Journal ArticleDOI
Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering
TL;DR: It is shown here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to Tunnel FET scaling.
Journal ArticleDOI
Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature
TL;DR: In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.