Journal ArticleDOI
RF Performance and Small-Signal Parameter Extraction of Junctionless Silicon Nanowire MOSFETs
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TLDR
In this article, the authors presented a radiofrequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field effect transistors (MOSFETs) using a 3D device simulator.Abstract:
This paper presents a radio-frequency (RF) model and extracted model parameters for junctionless silicon nanowire (JLSNW) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a 3-D device simulator. JLSNW MOSFETs are evaluated for various RF parameters such as cutoff frequency fT, gate input capacitance, distributed channel resistances, transport time delay, and capacitance by the drain-induced barrier lowering effect. Direct comparisons of high-frequency performances and extracted parameters are made with conventional silicon nanowire MOSFETs. A non-quasi-static RF model has been used, along with SPICE to simulate JLSNW MOSFETs with RF parameters extracted from 3-D-simulated Y-parameters. The results show excellent agreements with the 3-D-simulated results up to the high frequency of fT.read more
Citations
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Journal ArticleDOI
Effect of Band-to-Band Tunneling on Junctionless Transistors
Suresh Gundapaneni,Mohit Bajaj,Rajan K. Pandey,Kota V. R. M. Murali,Swaroop Ganguly,Anil Kottantharayil +5 more
TL;DR: In this paper, the authors evaluate the impact of band-to-band tunneling on the characteristics of n-channel junctionless transistors (JLTs) and present guidelines to optimize the device for high on-tooff current ratio.
Journal ArticleDOI
Effect of gate engineering in double-gate MOSFETs for analog/RF applications
TL;DR: It is demonstrated that TM-DG MOSFET can be a viable option to enhance the performance of SOI technology for high-frequency analog applications.
Journal ArticleDOI
A Junctionless Nanowire Transistor With a Dual-Material Gate
TL;DR: In this paper, a dual-material-gate junctionless nanowire transistor (DMG-JNT) was proposed and compared with a generic single-material gate JNT using 3D numerical simulations.
Journal ArticleDOI
A Dual-Material Gate Junctionless Transistor With High- $k$ Spacer for Enhanced Analog Performance
Ratul Kumar Baruah,Roy Paily +1 more
TL;DR: In this paper, the authors presented a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high-k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device.
Journal ArticleDOI
Semianalytical Model of the Subthreshold Current in Short-Channel Junctionless Symmetric Double-Gate Field-Effect Transistors
TL;DR: In this paper, a 2D semianalytical solution for the electrostatic potential valid for junctionless symmetric double-gate field-effect transistors in sub-threshold regime is proposed, which is based on the parabolic approximation for the potential and removes previous limitations.
References
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Operation and modeling of the MOS transistor
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Journal ArticleDOI
High Performance Silicon Nanowire Field Effect Transistors
TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI
Junctionless multigate field-effect transistor
Chi-Woo Lee,Aryan Afzalian,Nima Dehdashti Akhavan,Ran Yan,Isabelle Ferain,Jean-Pierre Colinge +5 more
TL;DR: In this article, the authors describe a metaloxide-semiconductor MOS transistor concept in which there are no junctions and the channel doping is equal in concentration and type to the source and drain extension doping.
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.