Proceedings ArticleDOI
Silicon-on-insulator 'gate-all-around device'
Jean-Pierre Colinge,M.-H. Gao,Albert Romano-Rodriguez,Herman Maes,Cor Claeys +4 more
- pp 595-598
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TLDR
In this paper, the authors describe the process fabrication and the electrical characteristics of an SOI MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it.Abstract:
Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >read more
Citations
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Patent
Multi-gate MOS transistor and method of manufacturing the same
TL;DR: In this article, two silicon fins are vertically stacked on a silicon on insulator (SOI) substrate, and four side surfaces of an upper silicon fin and three sides surfaces of a lower silicon fin are used as a channel.
Journal ArticleDOI
A low-frequency noise study of gate-all-around SOI transistors
TL;DR: In this paper, the low-frequency noise characteristics of both n- and p-type gate-all-around (GAA) MOS transistors are reported and compared with the noise behavior of conventional, partially depleted (PD) SOI transistors.
Journal Article
Temperature effects on Threshold Voltage and Mobility for Partially Depleted SOI MOSFET
Neha Goel,Ankit Tripathi +1 more
TL;DR: A detailed investigation of short-channel effects in advanced partially depleted SOI N-MOSFETs is done, which shows SOI devices from the same wafer can behave as fully or partially depleted according to the channel length.
Journal ArticleDOI
Low-Frequency Noise Characteristics in SONOS Flash Memory With Vertically Stacked Nanowire FETs
Tewook Bang,Byung-Hyun Lee,Choong-Ki Kim,Dae-Chul Ahn,Seung-Bae Jeon,Minho Kang,Jae-Sub Oh,Yang-Kyu Choi +7 more
TL;DR: In this paper, a vertically stacked nanowire (VS-NW) memory device is characterized in two different operational modes, an inversion-mode and a junctionless-mode (JM).
Journal ArticleDOI
Systematic electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process
Yongxun Liu,K. Ishii,Toshiyuki Tsutsumi,M. Masahara,Toshihiro Sekigawa,Kunihiro Sakamoto,H. Takashima,Hiromi Yamauchi,Eiichi Suzuki +8 more
TL;DR: In this article, the electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs fabricated by a wet process have been experimentally and systematically investigated.
References
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Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
T. Sekigawa,Y. Hayashi +1 more
Journal ArticleDOI
Modes of operation and radiation sensitivity of ultrathin SOI transistors
TL;DR: In this paper, the effects of radiation on threshold voltage, sub-threshold slope, and mobility in ultrathin, fully depleted silicon-on-insulator (SOI) transistors are discussed.
Journal ArticleDOI
Assessments of SOI technologies for hardening
TL;DR: In this paper, prospective results of a SIMOX technology prototype are presented, compared with those from the literature, based on SIMOX or other structures, and the advantages and weaknesses of these structures are discussed.
Journal ArticleDOI
A Fast and Precise Specimen Preparation Technique for TEM Investigation of Prespecified Areas of Semiconductor Devices
TL;DR: In this paper, a plan view and cross-section specimen preparation technique for the localized thinning of semiconductor devices for TEM investigation is presented, using an iterative ion milling procedure.