Proceedings ArticleDOI
Silicon-on-insulator 'gate-all-around device'
Jean-Pierre Colinge,M.-H. Gao,Albert Romano-Rodriguez,Herman Maes,Cor Claeys +4 more
- pp 595-598
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TLDR
In this paper, the authors describe the process fabrication and the electrical characteristics of an SOI MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it.Abstract:
Describes the process fabrication and the electrical characteristics of an SOI (silicon-on-insulator) MOSFET with gate oxide and a gate electrode not only on top of the active silicon film but also underneath it. Device fabrication is simple and necessitates only a single additional mask and etch step, compared to standard SOI processing. The device shows evidence of volume inversion (inversion is observed not only in surface channels, but through the entire thickness of the silicon film). Because of the presence of two channels and because of reduced carrier scattering within the bulk of the silicon film, the transconductance of the 'gate-all-around' device is more than twice that of a conventional SOI device, and its subthreshold slope is nearly 60 mV/decade at room temperature. >read more
Citations
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Journal ArticleDOI
Modeling of ultrathin double-gate nMOS/SOI transistors
TL;DR: In this paper, an analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices, which is based on Poisson's equation, containing both the doping impurity charges and the electron concentration.
Journal ArticleDOI
Modeling and Simulation of Single-Event Effects in Digital Devices and ICs
Daniela Munteanu,Jean-Luc Autran +1 more
TL;DR: In this article, the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits, with a special emphasis on the current challenges concerning the physical modeling of ultra-scaled devices (in the deca-nanometer range) and new device architectures (Silicon-on-insulator, multiple-gate, nanowire MOSFETs).
Patent
Doping of semiconductor fin devices
TL;DR: In this paper, the dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surfaces.
Journal ArticleDOI
Back-gated CMOS on SOIAS for dynamic threshold voltage control
TL;DR: A novel Silicon-On-Insulator-with-Active-Substrate (SOIAS)based technology was developed whereby a back-gate is used to control the threshold voltage of the front-gate and this concept was demonstrated on a selectively scaled CMOS process implementing discrete devices and ring oscillators.
Journal ArticleDOI
Externally Assembled Gate-All-Around Carbon Nanotube Field-Effect Transistor
TL;DR: In this article, a gate-all-around single-wall carbon nanotube field effect transistor (CNTF) is demonstrated. Butt et al. demonstrate the first successful experimental implementation of an off-chip gate and gate-dielectric assembly with subsequent deposition on a suitable substrate.
References
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Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
T. Sekigawa,Y. Hayashi +1 more
Journal ArticleDOI
Modes of operation and radiation sensitivity of ultrathin SOI transistors
TL;DR: In this paper, the effects of radiation on threshold voltage, sub-threshold slope, and mobility in ultrathin, fully depleted silicon-on-insulator (SOI) transistors are discussed.
Journal ArticleDOI
Assessments of SOI technologies for hardening
TL;DR: In this paper, prospective results of a SIMOX technology prototype are presented, compared with those from the literature, based on SIMOX or other structures, and the advantages and weaknesses of these structures are discussed.
Journal ArticleDOI
A Fast and Precise Specimen Preparation Technique for TEM Investigation of Prespecified Areas of Semiconductor Devices
TL;DR: In this paper, a plan view and cross-section specimen preparation technique for the localized thinning of semiconductor devices for TEM investigation is presented, using an iterative ion milling procedure.